Network Operation and Remote Control
R&S
®
FSMR3000
326
User Manual 1179.0116.02 ─ 02
Bit No.
Meaning
5
ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is set
and enabled in the event status enable register. Setting of this bit indicates a serious error which
can be specified in greater detail by polling the event status register.
6
MSS bit (main status summary bit)
The bit is set if the instrument triggers a service request. This is the case if one of the other bits
of this registers is set together with its mask bit in the service request enable register SRE.
7
STATus:OPERation
status register summary bit
The bit is set if an
EVENt
bit is set in the
OPERation
status register and the associated
ENABle
bit is set to 1. A set bit indicates that the instrument is just performing an action. The
type of action can be determined by querying the
STATus:OPERation
status register.
11.2.2.2
IST flag and parallel poll enable register (PPE)
As with the SRQ, the IST flag combines the entire status information in a single bit. It
can be read by means of a parallel poll or using the command
The parallel poll enable register (PPE) determines which bits of the STB contribute to
the IST flag. The bits of the STB are "ANDed" with the corresponding bits of the PPE,
with bit 6 being used as well in contrast to the SRE. The IST flag results from the
"ORing" of all results. The PPE can be set using commands
mand *PRE?.
11.2.2.3
Event status register (ESR) and event status enable register (ESE)
The ESR is defined in IEEE 488.2. It can be compared with the
EVENt
part of a SCPI
register. The event status register can be read out using command
.
The ESE corresponds to the
ENABle
part of a SCPI register. If a bit is set in the ESE
and the associated bit in the ESR changes from 0 to 1, the ESB bit in the STB is set.
The ESE register can be set using the command
*ESE?
.
Table 11-4: Meaning of the bits used in the event status register
Bit No.
Meaning
0
Operation Complete
This bit is set on receipt of the command *OPC exactly when all previous commands have been
executed.
1
Not used
2
Query Error
This bit is set if either the controller wants to read data from the instrument without having sent a
query, or if it does not fetch requested data and sends new instructions to the instrument
instead. The cause is often a query which is faulty and hence cannot be executed.
Status Reporting System