NXP Semiconductors MPC5644A, Справочное руководство, Страница: 833 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 833
middle-level requests arrive, and there are also three low level pending service requests. Thus, time slot
seven of cycle B and time slot one of cycle C are passed to the middle-level which is the next priority level
after high. Time slots two and three of cycle C are passed to the low level which contains the three
remaining channel service requests. At time slot three of cycle C the last low level request is serviced, and
the Scheduler passes to idle state. At this point the cycle C is truncated and the Scheduler passes to time
slot one of cycle D.
24.5.3.2.2 Priority passing disabling
The priority passing scheme allows a case where a high priority channel looses to a lower priority one right
after another lower priority has been serviced, exemplified in the Cycle D on
Figure 24-32 . A middle
priority channel wins time slot 1 due to priority passing from high to middle. While it is being serviced,
two new service requests arrive, one high and one middle priority. The high priority request looses to the
middle one on next time slot 2 by default priority assignment.
This priority inversion can be avoided by setting the ETPU_ECR bit SPPDIS (see Section 24.4.2.5,
ETPU_ECR – eTPU Engine Configuration Register ), which disables the priority passing mechanism.
When priority passing is disabled, at the end of the thread the slot number is incremented until a time slot
that matches the priority of one of the requesting channel(s). The time slot advance takes no extra clocks.
If no channel requests service, the time slot counter stays at time slot 1. The priority selection scheme with
disabled priority passing is summarized in
Table 24-40 .
An example of the priority passing disabling scheme is illustrated in Figure 24-33 . The sequence of service
requests is the same as in the example of Figure 24-32 , and although the time slot incrementing differs, the
priorities granted are the same for cycle B. Cycle C has one of the low priority channels serviced before
the second middle one. Cycle D, however, no longer has the priority inversion.
In cycle B, after the time slot 2 only a low priority request remains, so the time slot count advances directly
to 4, which has a low priority assigned. Time slot keeps on 4 for the next service, as only a low priority
request remains also, and only time slot 4 is assigned to low. Two high priority services contend for the
next time slot 5 (assigned to High). The second high priority channel is serviced on the next time slot,
jumped to 7 because there is no middle request, ending cycle B. Cycle C starts with time slot 2, as there
Table 24-40. Priority Passing Disabling
At the end
of time
slot
servicin
g
priority
if any
request
of priority
service
it on time
slot
else
if any
request
of priority
service
it on time
slot
else
if any
request
of priority
service
it on time
slot
1 High Medium 2 High 3 Low 4
2 Medium High 3 Low 4 Medium 6
3 High Low 4 High 5 Medium 6
4 Low High 5 Medium 6 Low 4
5 High Medium 6 High 7 Low 4
6 Medium High 7 Medium 2 Low 4
7 High High 1 Medium 2 Low 4