NXP Semiconductors MPC5644A, Справочное руководство, Страница: 1583 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1583
33.6.9.4 FIFO reception
The FIFO reception is a CC internal operation.
A message frame reception is directed into the FIFO, if no individual message buffer is assigned for
transmission or subscribed for reception for the current slot. In this case the FIFO filter path shown in
Figure 33-148 is activated.
If the FIFO filter path indicates that the received frame has to be appended to the FIFO and the FIFO is
not full, the CC writes the received frame header into the message buffer header field indicated by the CC
internal FIFO write index. The frame payload data are written into the corresponding message buffer data
field. If the status of the received frame indicates a valid non-null frame, the slot status information is
written into the message buffer header field and the CC internal FIFO write index is updated by 1 and the
FIFO fill level FLA (FLB) in the
Receive FIFO Fill Level and POP Count Register (FR_RFFLPCR) is
incremented.If the status of the received frame indicates an invalid or null frame, the frame is not appended
to the FIFO.
33.6.9.5 FIFO almost-full interrupt generation
If the FIFO fill level FLA (FLB) is updated after a frame reception and exceeds the FIFO watermark level
WM, that is, FLA > WM
A
(FLB > WM
B
), then the FIFO almost-full interrupt flag FR_GIFER[FAFAIF]
(FR_GIFER[FAFBIF]) is asserted.If the periodic timer expires, and FIFOA (FIFOB) is not empty, that is,
FLA > 0 (FLB > 0), then the FIFO almost-full interrupt flag FR_GIFER[FAFAIF] (FR_GIFER[FAFBIF])
is asserted.
33.6.9.6 FIFO overflow error generation
If the FIFOA (FIFOB) is full, that is, FLA = FIFO_DEPTH
A
(FLB = FIFO_DEPTH
B
) and the conditions
for a FIFO reception as described in Section 33.6.9.4, FIFO reception ” are fulfilled, then the FIFO
overflow error flag FR_CHIERFR[FOVA_EF] (FR_CHIERFR[FOVB_EF]) is asserted.
33.6.9.7 FIFO message access
The FIFOA (FIFOB) contains valid messages if the FIFO fill level FLA (FLB) is greater than 0. The
Receive FIFO A Read Index Register (FR_RFARIR) ( Receive FIFO B Read Index Register
(FR_RFBRIR) ) pointing to a message buffer with valid content and the oldest frames stored in the FIFO.
If the FIFO fill level FLA (FLB) is 0, than the FIFOA (FIFOB) contains no valid messages and the Receive
FIFO A Read Index Register (FR_RFARIR) ( Receive FIFO B Read Index Register (FR_RFBRIR) )
pointing to a message buffer with invalid content. In this case the application must not read data from the
FIFO.
To access the oldest message in the FIFOA (FIFOB), the application first reads the read index RDIDX out
of the
Receive FIFO A Read Index Register (FR_RFARIR) ( Receive FIFO B Read Index Register
(FR_RFBRIR) ). This read index points to the message buffer header field of the oldest message buffer that
contains valid received message data. The application can access the message data as described in
Section 33.6.3.3, Receive FIFO”. When the application has read the message buffer data and status
information, it can update the FIFO as described in Section 33.6.9.8, FIFO update ”.