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Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1106
Freescale Semiconductor
when the CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer or a not -full
external CBuffer.
The EQADC clears the SSS bit and stops transferring commands from a TRIGGERED CFIFO when an
asserted EOQ bit is encountered or when CFIFO status changes from TRIGGERED due to the detection
of a closed gate. If a closed gate is detected while no command transfers are taking place and the CFIFO
status is TRIGGERED, the CFIFO status is immediately changed to IDLE, the SSS bit is negated, and the
PF flag is asserted. If a closed gate is detected during the serial transmission of a command to the external
device, it will have no effect on the CFIFO status until the transmission completes. Once the transmission
is completed, the TC_CF counter is updated, the SSS bit is negated, the PF flag is asserted, and the CFIFO
status is changed to IDLE. An asserted SSS bit and a level trigger are required to restart the CFIFO.
Command transfers will restart from the point they have stopped.
If the gate closes and opens during the same serial transmission of a command to the external device, it
will have no effect on the CFIFO status or on the PF flag, but the TORF flag will become asserted as was
exemplified in
. Therefore, closing the gate for a period less than a serial transmission time
interval does not guarantee that the closure will affect command transfers from a CFIFO.
The Pause bit has no effect in single-scan level-trigger mode.
25.6.4.6.3
Continuous-Scan Mode
In continuous-scan mode, multiple passes looping through a sequence of command messages in a CQueue
are executed. When a CFIFO is programmed for a continuous-scan mode, the SSE bit in the
Section 25.5.2.7, EQADC CFIFO Control Registers (EQADC_CFCR)
Continuous-Scan Software Trigger
When a CFIFO is programmed to continuous-scan software trigger mode, the CFIFO is triggered
immediately. The CFIFO commands start to be transferred when the CFIFO becomes the highest priority
CFIFO using a not-full on-chip CBuffer or an not-full external CBuffer. When a CFIFO is programmed to
run in continuous-scan software trigger mode, the EQADC will not halt transfers from the CFIFO until the
CFIFO operation mode is modified to disabled or a higher priority CFIFO preempts it. Although command
transfers will not stop upon detection of an asserted EOQ bit, the EOQF is set and, if enabled, an EOQ
interrupt request is generated.
The Pause bit has no effect in continuous-scan software trigger mode.
Continuous-Scan Edge Trigger
When rising, falling, or either edge trigger mode is selected for a CFIFO, a corresponding edge on the
associated ETRIG signal places the CFIFO in TRIGGERED state. The CFIFO commands start to be
transferred when the CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer or an
not-full external CBuffer
When an EOQ or a Pause is encountered, the EQADC halts command transfers from the CFIFO and, if
enabled, the appropriate interrupt requests are generated. Another edge trigger event is required to resume
command transfers but no software involvement is required to rearm the CFIFO in order to detect such
event.
Содержание MPC5644A
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