FXTH870xD
Sensors
72
Freescale Semiconductor, Inc.
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow.
An alternative approach is to reset the TPM1 counter before writing to the TPM1 modulo registers to avoid confusion about when
the first counter overflow will occur.
9.4.4
Timer Channel 0 Status and Control Register (TPM1C0SC)
TPM1C0SC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel
configuration, and pin function.
$0014
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 47. Timer Counter Modulo Register Low (TPM1MODL)
$0015
7
6
5
4
3
2
1
0
R
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
W
Reset
0
0
0
0
0
0
0
0
= Reserved
Figure 48. Timer Channel 0 Status and Control Register (TPM1C0SC)
Table 49. TPM1C0SC Register Field Descriptions
Field
Description
7
CH0F
Channel 0 Flag
— When channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel
n pin. When channel 0 is an output compare or edge-aligned PWM channel, CH0F is set when the value in the TPM1 counter
registers matches the value in the TPM1 channel 0 value registers. This flag is seldom used with center-aligned PWMs because
it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle
period.
A corresponding interrupt is requested when CH0F is set and interrupts are enabled (CH0IE = 1). Clear CH0F by reading
TPM1C0SC while CH0F is set and then writing a 0 to CH0F. If another interrupt request occurs before the clearing sequence
is complete, the sequence is reset so CH0F would remain set after the clear sequence was completed for the earlier CH0F.
This is done so a CH0F interrupt request cannot be lost by clearing a previous CH0F. Reset clears CH0F. Writing a 1 to CH0F
has no effect.
0
No input capture or output compare event occurred on channel 0
1
Input capture or output compare event occurred on channel 0
6
CH0IE
Channel 0 Interrupt Enable
— This read/write bit enables interrupts from channel 0. Reset clears CH0IE.
0
Channel 0 interrupt requests disabled (use software polling)
1
Channel 0 interrupt requests enabled
5
MS0B
Mode Select B for TPM1 Channel 0
— When CPWMS = 0, MS0B = 1 configures TPM1 channel 0 for edge-aligned PWM
mode. For a summary of channel mode and setup controls, refer to
Table 50
.
4
MS0A
Mode Select A for TPM1 Channel 0
— When CPWMS = 0 and MS0B = 0, MS0A configures TPM1 channel 0 for input capture
mode or output compare mode. Refer to
Table 50
for a summary of channel mode and setup controls.
3:2
ELS0[B:A]
Edge/Level Select Bits
— Depending on the operating mode for the timer channel as set by CPWMS:MS0B:MSnA and shown
in
Table 50
, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven
in response to an output compare match, or select the polarity of the PWM output.
Setting ELS0B:ELS0A to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a
general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin.
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