FXTH870xD
Sensors
90
Freescale Semiconductor, Inc.
11.5
PWU Wakeup Status Register - PWUS
The PWUS register shows the current status of the two PWU counters as described in
Figure 63
. The counter contents are
captured when the register is read.
11.6
Functional Modes
PWU module will work in each of the MCU operating modes as follows:
11.6.1
RUN Mode
If the module generates a wakeup interrupt the PC (Program Counter) will be redirected to the wakeup timer interrupt vector. The
WUF flag will be set to indicate wakeup timer interrupt; write 1 to WUFACK to clear this flag.
If the module generates a reset the PC will be redirected to the reset vector. The PRF flag will be set to indicate periodic reset;
write 1 to PRFACK to clear this flag.
All registers will continue to hold their programmed values after interrupt or reset is taken.
11.6.2
STOP4 Mode
If the module generates a wakeup interrupt the bus and core clocks will be restarted and the PC will be redirected to the wakeup
timer interrupt vector. The WUF flag will be set to indicate wakeup timer interrupt, write 1 to WUFACK to clear this flag.
If the module generates a periodic reset the bus and core clocks will be restarted and the PC will be redirected to the reset vector.
The PRF flag will be set to indicate periodic reset; write 1 to PRFACK to clear this flag.
All registers will continue to hold their programmed values after interrupt or reset is taken.
11.6.3
STOP1 Mode
If the module generates a wakeup interrupt the module will cause the MCU to exit the power saving mode as a POR. MCU will
have the wakeup interrupt pending and once CLI opcode is executed PC will be redirected to wakeup interrupt vector address.
The WUF flag will be set to indicate wakeup timer interrupt, write 1 to WUFACK to clear this flag.
If the module generates a periodic reset the module will cause the MCU to exit the power saving mode as a POR. The PRF flag
will be set to indicate periodic reset; write 1 to PRFACK to clear this flag. The SRS register will have just the POR bit set.
In this STOP mode exit all registers will continue to hold their programmed values.
11.6.4
Active BDM/Foreground Commands
The PWU is frozen in ACTIVE BACKGROUND mode or executing foreground commands, so PWU counters will also be stopped.
Normal PWU operation will resume as MCU exits BDM or foreground command is finished.
$001F
Bit 7
6
5
4
3
2
1
Bit 0
R
PSEL
0
CSTAT
W
RESET:
0
-
-
-
-
-
-
-
= Reserved
Figure 64. PWU Wakeup Status Register (PWUS)
Table 58. PWUS Register Field Descriptions
Field
Description
7
PSEL
Page Selection
— The PSEL read/write bit selects whether the other bits are read from the WUT or PRST counters. This bit is
cleared by a power on reset that is not created by an exit from the STOP mode, but is unaffected by other resets.
0
CSTAT = WUT counter status
1
CSTAT = PRST counter status
6
unused
Unused
— An unused bit that always reads as a logical zero.
5:0
CSTAT
Counter Status
— These read-only bits show the status of the counter selected by the PSEL bit. The effects of any reset on
these bits depends on how the reset affects the selected counter. Reading these counters immediately after a WUF or PRF
generated flag will return zero contents.
Содержание FXTH870 D Series
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