NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
40 Freescale Semiconductor, Inc.
5.11.3 System Operation Register 2 (SIMOPT2)
The following clock source and frequency selections are available using the system option register 2 as shown in Figure 23 .
6
COPCLKS
COP Clock Select — This control bit selects the clock source for the COP watchdog timer. This bit is a write-once bit so that
only the first write after reset is honored. This bit is cleared by an MCU reset.
0
Select the LFO oscillator output.
1 Select the CPU bus clock.
5
STOPE
STOP Mode Select — This control bit enables/disables the STOP instruction to enter a STOP mode defined by the SPMSCR2
register. This bit is a write-once bit so that only the first write after reset is honored. This bit is cleared by an MCU reset.
0
Disable STOP modes.
1 Enable STOP modes.
4
RFEN
RF Module Enable — This bit enables or disables the RF module. This bit is not affected by any reset or power on after STOP
exit. It is only initialized at the first power up. This bit can be written anytime.
1
RF module enabled.
0 RF module disabled.
3
TRE
Temperature Restart Enable — This control bit enables the temperature restart circuit to interrupt the MCU after being
shutdown at either a very high or very low temperature. This bit is cleared by an MCU reset.
0
Temperature restart disabled.
1 Temperature restart enabled.
2
TRH
Temperature Restart Level — This control bit selects whether the temperature restart circuit will interrupt the MCU after being
shutdown on returning from either a very high or very low temperature. This bit is cleared by an MCU reset.
0
Temperature restart interrupts MCU on return from a very low temperature.
1 Temperature restart interrupts MCU on return from a very high temperature.
1
BKGDPE
BKGD Pin Enable — BKGDPE can be used to allow the BKGD/PTA4 pin to be shared in applications as an input-only general
purpose I/O pin:
0
BKGD function disabled, PTA4 enabled.
1 BKGD function enabled, PTA4 disabled.
0
Reserved
Reserved register bit, always reads 1.
$1803 Bit 7 6 5 4 3 2 1 Bit 0
R
0 COPT[2:0] LFOSEL TCLKDIV BUSCLKS[1:0]
W
RESET:
0 1 1 1 0 0 0 0
Figure 23. System Option Register 2 (SIMOPT2)
Table 27. SIMOPT2 Register Field Descriptions
Field Description
7
Unused
Unused Bit — This bit is unused and reads as a logic zero.
6:4
COPT[2:0]
COP Watchdog Time Out — These control bits select the timeout period for the COP watchdog timer as given in Table 18 .
These bits are set by an MCU reset to select the longest watchdog timeout period. These bits are write-once after power up.
3
LFOSEL
TPM1 Channel 0 Clock Source — This bit determines which signal is connected to the TPM1 Channel 0, see Section 9 .
0 Select clock input driven by PTA2.
1 Select clock input driven by the LFO.
2
TCLKDIV
TPM1 Channel 0 CLock Source Divider — The divider for the clock Source for TPM1 Channel 0, see Section 9 .
0 Select RFM Dx clock source divided by 1.
1 Select RFM Dx clock source divided by 8.
Table 26. SIMOPT1 Register Field Descriptions (continued)
Field Description