NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
141
Figure 115. BDC Host-to-Target Serial Bit Timing
Figure 116 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD/PTA4 to the perceived start of the bit time in the target
MCU. The host holds the BKGD/PTA4 pin low long enough for the target to recognize it (at least two target BDC cycles). The
host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived
start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time.
Figure 116. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 117 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD/PTA4 to the start of the bit time as perceived by the
target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic
0, it drives the BKGD/PTA4 pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host
samples the bit level about 10 cycles after starting the bit time.
EARLIEST START
TARGET SENSES BIT LEVEL
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED START
OF BIT TIME
OF NEXT BIT
HOST SAMPLES BKGD/PTA4 PIN
10 CYCLES
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD/PTA4 PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
BKGD/PTA4 PIN
R-C RISE
10 CYCLES
EARLIEST START
OF NEXT BIT