FXTH870xD
Sensors
Freescale Semiconductor, Inc.
101
12.17.2 LF Control Register 2 (LFCTL2)
LFCTL2 contains the selection bits for the length of the LF sampling ON time and the time interval between samples as shown
in
.
$0021
Bit 7
6
5
4
3
2
1
Bit 0
R
LFSTM[3:0]
LFONTM[3:0]
W
Reset:
0
1
1
0
0
0
0
0
Figure 76. LFR Control Register 2 (LFCTL2)
Table 60. LFCTL2 Register Field Descriptions
Field
Description
7:4
LFSTM
[3:0]
LF Sampling Time Interval Select
— These read/write control bits select the length of time between when the LFR input detector
is turned on as set by the LFONTM bits in LFCTL2 register. The initial sampling interval starts with the LFO clock following a write
to these bits. A reset of the LFR results in the value being set to binary 0110.
0000 Continuous ON mode (see
0001 Sampled decoding mode every 16 LFO clock periods (16 milliseconds nominal)
0010 Sampled decoding mode every 32 LFO clock periods (32 milliseconds nominal)
0011 Sampled decoding mode every 64 LFO clock periods (64 milliseconds nominal)
0100 Sampled decoding mode every 128 LFO clock periods (128 milliseconds nominal)
0101 Sampled decoding mode every 256 LFO clock periods (256 millisecond nominal)
0110 Sampled decoding mode every 512 LFO clock periods (512 milliseconds nominal)
0111
Sampled decoding mode every 1024 LFO clock periods (1024 milliseconds nominal)
1000 Sampled decoding mode every 2048 LFO clock periods (2048 milliseconds nominal)
1001 Sampled decoding mode every 4096 LFO clock periods (4096 milliseconds nominal)
1010-1xxxContinuous ON mode (see
3:0
LFONTM
[3:0]
LF Sampling ON
Time Select
— These read/write control bits select the length of time that the LFR input
detector is turned on at the beginning of each sampling interval set by the LFSTM bits. This ON time is the net sampling time
with any initialization time (maximum of 2 ms) included in the OFF time prior to the sample ON time (see
Figure 77
). If a signal
is successfully detected, the length of time the detector remains ON depends on the operating mode. In carrier detect mode
(CARMOD = 1) the detector will be turned off early if the evaluation of the carrier signal is completed before the end of the
scheduled ON time. In data receive mode (CARMOD = 0) the detector will remain ON until the end of the message, an error is
detected or timeout occurrence. Reset forces the LFONTM bits
to 0:0:0.
0000 1 LFO clock cycle (1 millisecond nominal)
0001 2 LFO clock cycle (2 milliseconds nominal)
0010 4 LFO clock cycle (4 milliseconds nominal)
0011 8 LFO clock cycle (8 milliseconds nominal)
0100 16 LFO clock cycle (16 milliseconds nominal)
0101 32 LFO clock cycle (32 milliseconds nominal)
0110 64 LFO clock cycle (64 milliseconds nominal)
0111
128 LFO clock cycle (128 milliseconds nominal)
1000 256 LFO clock cycle (256 milliseconds nominal)
1001 512 LFO clock cycle (512 milliseconds nominal)
1010 1024 LFO clock cycles (1024 milliseconds nominal)
1011 1024 LFO clock cycles (1024 milliseconds nominal)
11xx
1024 LFO clock cycles (1024 milliseconds nominal)
Note:
The LFONTM selected time must be less than the LFSTM selected time, otherwise the Continuously ON mode is present.
Содержание FXTH870 D Series
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