NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
126 Freescale Semiconductor, Inc.
13.13 RFM Control Register 4 - RFCR4
The RFCR4 register contains eight control bits to set the initial and interframe timing base timing variable as described in
Figure 103 . A RFMRST signal clears the RFBT[7:0] bits.
13.14 RFM Control Register 5 - RFCR5
The RFCR5 register contains eight control bits to set the initial and interframe random timing variable as described in Figure 104 .
A RFMRST signal clears the LFSR[6:0] bits causing the random time variable to be ignored.
$0034 Bit 7 6 5 4 3 2 1 Bit 0
R
RFBT[7:0]
W
RFMRST:
1 0 0 0 0 0 0 0
Figure 103. RFCR4 Register - Base Time Variable
Table 78. RFCR4 Field Descriptions
Field Description
7:0
RFBT
[7:0]
Base Timer - The RFBT[7:0] control bits select the interframe timing between multiple frames of transmission. The base time
value is equal to a nominal one millisecond for each count of the RFBT[7:0] bits. The RFBT[7:0] control bits are cleared by the
RFMRST signal and must be set to either 0 or between 5 and 255.
$0035 Bit 7 6 5 4 3 2 1 Bit 0
R
BOOST LFSR[6:0]
W
RFMRST:
0 0 0 0 0 0 0 0
Figure 104. RFCR5 Register - Pseudo-Random Time Variable
Table 79. RFCR5 Field Descriptions
Field Description
7
BOOST
BOOST - This bit controls the VCO power consumption in order to decrease the phase noise required by the Japanese
regulation. The BOOST control bit is cleared by the RFMRST signal.
0
The VCO runs at its lower power consumption level (higher phase noise).
1 The VCO runs at its higher power consumption level (lower phase noise).
6:0
LFSR[6:0]
Pseudo-Random Timer - The LFSR[6:0] bits select the current seed value of the LFSR when enabling pseudo-random timing
intervals when any of the LFSR[6:0] bits are set. The value written to this register is loaded into the actual LFSR when the SEND
bit is set. The time value is equal to a nominal one millisecond for each count of the resulting LFSR[6:0] bits.
A value of $00 placed in the LFSR causes the LFSR to stay at the $00 state on each clocking of the LFSR. To cause the LFSR
to cycle through its pseudo-random number sequence requires that any value other than $00 be written to the LFSR[6:0] bits.
Note: If RFBT[7:0] and RFFT[5:0] are both set to non-zero, and LFSR[6:0] is set to 0x00, the system will decrement both RFBT
and RFFT simultaneously rather than serially, such that the effective Interframe Interval will be equal to the larger of RFBT or
RFFT settings.