FXTH870xD
Sensors
36
Freescale Semiconductor, Inc.
5.6
Low-Voltage Detect (LVD) System
The FXTH870xD includes a system to detect low voltage conditions in order to protect memory contents and control MCU system
states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and an LVD circuit with a user
selectable trip voltage, either high (V
LVDH
) or low (V
LVDL
). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip
voltage is selected by LVDV in SPMSC3. The LVD is disabled upon entering any of the STOP modes unless the LVDSE bit is
set. If LVDSE and LVDE are both set, then the MCU cannot enter STOP1.
5.6.1
Power-On Reset Operation
When power is initially applied to the FXTH870xD, or when the supply voltage drops below the V
POR
level, the POR circuit will
cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in reset until the supply has risen above the
level determined by LVDV bit. Both the POR bit and the LVD bit in SRS are set following a POR.
5.6.2
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition has occurred by setting LVDRE to 1
when the supply voltage has fallen below the level determined by LVDV bit. After an LVD reset has occurred, the LVD system will
hold the FXTH870xD in reset until the supply voltage has risen above the level determined by LVDV bit. The threshold for falling
and rising differ by a small amount of hysteresis. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.6.3
LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE set, LVDIE set, and
LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.6.4
Low-Voltage Warning (LVW)
The LVD system has a low voltage warning flag, LVWF, to indicate to the user that the supply voltage is approaching, but is still
above, the LVD reset voltage. The LVWF can be reset by writing a logical one to the LVWACK bit. The LVW does not have an
interrupt associated with it. There are two user selectable trip voltages for the LVW as selected by LVWV in SPMSC3. The LVWF
is set when the supply voltage falls below the selected level and cannot be reset until the supply voltage has risen above the
selected level. The threshold for falling and rising differ by a small amount of hysteresis.
5.7
System Clock Control
Several clock rate selections are possible with the FXTH870xD using the BUSCLKS[1:0] control bits to select the clock frequency
division of the HFO as given in
. These bits are cleared by any MCU reset.
5.8
Keyboard Interrupts
The keyboard interrupts can be used to wake the MCU. These are assigned to specific general I/O pins as given in
Table 22
.
Table 21. HFO Frequency Selections
BUSCLKS1
BUSCLKS0
HFO Frequency
(MHz)
CPU Bus Frequency (MHz)
0
0
8
4
0
1
4
2
1
0
2
1
1
1
1
0.5
Table 22. Keyboard Interrupt Assignments
KBI
Pin
Pin Function
0
PTA0
General I/O
1
PTA1
General I/O
2
PTA2
General I/O
3
PTA3
General I/O
Содержание FXTH870 D Series
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