NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
145
15.3.2 BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to
user programs because it is not located in the normal memory map of the MCU.
7 6 5 4 3 2 1 0
R
ENBDM
BDMACT
BKPTEN FTS CLKSW
WS WSF DVF
W
Normal Reset
0 0 0 0 0 0 0 0
Reset in
Active BDM:
1 1 0 0 1 0 0 0
= Reserved
Figure 118. BDC Status and Control Register (BDCSCR)
Table 91. BDCSCR Register Field Descriptions
Field Description
7
ENBDM
Enable BDM (Permit ACTIVE BACKGROUND Mode) — Typically, this bit is written to 1 by the debug host shortly after the
beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it.
0
BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow ACTIVE BACKGROUND mode commands
6
BDMACT
BACKGROUND Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
5
BKPTEN
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and
BDCBKPT match register are ignored.
0
BDC breakpoint disabled
1 BDC breakpoint enabled
4
FTS
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match
register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be
tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters ACTIVE BACKGROUND mode
rather than executing the tagged opcode.
0
Tag opcode at breakpoint address and enter ACTIVE BACKGROUND mode if CPU attempts to execute that instruction
1 Breakpoint match forces ACTIVE BACKGROUND mode at next instruction boundary (address need not be an opcode)
3
CLKSW
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock source.
0 Alternate BDC clock source
1 MCU bus clock
2
WS
WAIT or STOP Status — When the target CPU is in WAIT or STOP mode, most BDC commands cannot function. However,
the BACKGROUND command can be used to force the target CPU out of WAIT or STOP and into ACTIVE BACKGROUND
mode where all BDC commands work. Whenever the host forces the target MCU into ACTIVE BACKGROUND mode, the host
should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands.
0
Target CPU is running user application code or in ACTIVE BACKGROUND mode (was not in WAIT or STOP mode when
BACKGROUND became active)
1
Target CPU is in WAIT or STOP mode, or a BACKGROUND command was used to change from WAIT or STOP to ACTIVE
BACKGROUND mode
1
WSF
WAIT or STOP Failure Status — This status bit is set if a memory access command failed due to the target CPU executing a
WAIT or STOP instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to
get out of WAIT or STOP mode into ACTIVE BACKGROUND mode, repeat the command that failed, then return to the user
program. (Typically, the host would restore CPU registers and stack values and re-execute the WAIT or STOP instruction.)
0
Memory access did not conflict with a WAIT or STOP instruction
1 Memory access command failed because the CPU entered WAIT or STOP mode
0
DVF
Data Valid Failure Status — This status bit is not used in the MC9S08RA16 because it does not have any slow access
memory.
0
Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access