NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
41
5.11.4 System Power Management Status and Control 1 Register (SPMSC1)
Figure 24. System Power Management Status and Control 1 Register (SPMSC1)
1:0
BUSCLKS
[1:0]
Bus Clock Select — Bus clock frequency selection by changing HFO FLL ratio as shown in Figure 2 . The bus clock frequency
is always the HFO frequency divided by two. These bits are cleared by a reset and can be written at any time.
00 Bus Frequency = 4 MHz (HFO = 8 MHz)
01 Bus Frequency = 2 MHz (HFO = 4 MHz)
10 Bus Frequency = 1 MHz (HFO = 2 MHz)
11 Bus Frequency = 0.5 MHz (HFO = 1 MHz)
$1809
7 6 5 4 3 2
1
(1)
1. Bit 1 is a reserved bit that must always be written to 0.
0
R
LVDF 0
LVDIE LVDRE
(2)
2. This bit can be written only one time after reset. Additional writes are ignored.
LVDSE LVDE
(2)
0 BGBE
W LVDACK
Reset:
0 0 0 1 1 1 0 0
= Reserved
Table 28. SPMSC1 Register Field Descriptions
Field Description
7
LVDF
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDACK
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear
LVDF). Reads always return logic 0.
5
LVDIE
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling)
1 Request a hardware interrupt when LVDF = 1
4
LVDRE
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset (provided LVDE
= 1).
0
LVDF does not generate hardware resets
1 Force an MCU reset when LVDF = 1
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function
operates when the MCU is in STOP mode.
0
Low-voltage detect disabled during STOP mode
1 Low-voltage detect enabled during STOP mode
2
LVDE
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation of other bits in
this register.
0
LVD logic disabled
1 LVD logic enabled
0
Reserved
Reserved Bit — This bit is reserved should not be altered by the user. Any read returns a logical zero. Any write should be a
logical zero.
0
BGBE
Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer for the bandgap voltage reference for use by the
ADC module on one of its internal channels.
0
Bandgap buffer disabled
1 Bandgap buffer enabled
Table 27. SIMOPT2 Register Field Descriptions (continued)
Field Description