FXTH870xD
Sensors
Freescale Semiconductor, Inc.
73
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to
get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration
bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior.
9.4.5
Timer Channel Value Registers (TPM1C0VH:TPM1C0VL)
These read/write registers contain the captured TPM1 counter value of the input capture function or the output compare value
for the output compare or PWM functions. The channel value registers are cleared by reset.
In input capture mode, reading either byte (TPM1C0VH or TPM1C0VL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPM1C0SC
register is written.
In output compare or PWM modes, writing to either byte (TPM1C0VH or TPM1C0VL) latches the value into a buffer. When both
bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching
mechanism may be manually reset by writing to the TPM1C0SC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations.
Table 50. Mode, Edge, and Level Selection
CPWMS
MS0B:MS0A
ELS0B:ELS0A
Mode
Configuration
X
XX
00
Pin not used for TPM1 channel; use as an external clock for the TPM1 or revert
to general-purpose I/O
0
00
01
Input capture
Capture on rising edge only
10
Capture on falling edge only
11
Capture on rising or falling edge
01
00
Output compare
Software compare only
01
Toggle output on compare
10
Clear output on compare
11
Set output on compare
1X
10
Edge-aligned
PWM
High-true pulses (clear output on compare)
X1
Low-true pulses (set output on compare)
1
XX
10
Center-aligned
PWM
High-true pulses (clear output on compare-up)
X1
Low-true pulses (set output on compare-up)
$0016
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Reset
0
0
0
0
0
0
0
0
Figure 49. Timer
Channel 0 Value Register High (TPM1C0VH)
$0017
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 50. Timer
Channel 0 Value Register Low (TPM1C0VL)
Содержание FXTH870 D Series
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