MS51
Nov. 28, 2019
Page
62
of 491
Rev 1.00
MS51
32K
SE
RIES
TE
CHNICAL RE
F
EREN
CE MA
N
UAL
CKCON
– Clock Control
Register
SFR Address
Reset Value
CKCON
8EH, Page0
0000_0000b
7
6
5
4
3
2
1
0
-
PWMCKS
-
T1M
T0M
-
CLOEN
-
-
R/W
-
R/W
R/W
-
R/W
-
Bit
Name
Description
6
PWMCKS
PWM clock source select
0 = The clock source of PWM is the system clock F
SYS
.
1 = The clock source of PWM is the overflow of Timer 1.
4
T1M
Timer 1 clock mode select
0 = The clock source of Timer 1 is the system clock divided by 12. It maintains standard 8051
compatibility.
1 = The clock source of Timer 1 is direct the system clock.
3
T0M
Timer 0 clock mode select
0 = The clock source of Timer 0 is the system clock divided by 12. It maintains standard 8051
compatibility.
1 = The clock source of Timer 0 is direct the system clock.
1
CLOEN
System clock output enable
0 = System clock output Disabled.
1 = System clock output Enabled from CLO pin
Note:
CLO pin decide by AUXR5.7.
