MS51
Nov. 28, 2019
Page
451
of 491
Rev 1.00
MS51
32K
SE
RIES
TE
CHNICAL RE
F
EREN
CE MA
N
UAL
ADCCON3
– ADC Control 3
Register
SFR Address
Reset Value
ADCCON3
86H, Page 2
0000_0000 b
7
6
5
4
3
2
1
0
-
-
HIE
CONT
ADCAQT1[2:0]
SLOW
-
-
R/W
R/W
R/W
R/W
Bit
Name
Description
5
HIE
ADC Half Done Interrupt Enable
0 = ADC interrupt is not set while half of A/D conversions are complete in continue mode
1 = ADC interrupt is set while half of A/D conversions are complete in continue mode
4
CONT
ADC Continue Sampling select
0 = ADC single sampling, ADC interrupt is set while an A/D conversion is completed
1 = ADC continue sampling. ADC interrupt is set while total A/D conversions are completed
3:1
ADCAQT1
ADC acquisition time 1
This 3-bit field decides the acquisition time for ADC AIN9~AIN15 sampling, following by equation
below:
ADC acquisition time =.
ADCAQT
F
6
ADCAQT1
*
4
, F
ADCAQT
is defined in ADCDIV (ADCCON2[3:1])
The default and minimum acquisition time is 6 ADC clock cycles. Note that this field should not
be changed when ADC is in converting.
0
SLOW
ADC Slow Speed Selection
This bit is used to select ADC low speed.
0 = ADC convert time is high speed 1400ns, F
ADC
= 714 ksps
1 = ADC convert time is low speed 4750ns, F
ADC
= 215 ksps,
Note1 : slow speed ADC convert time will improvement ADC convert performance when VDD is
under 2.5V.
Note2: AUXR1.4 (SLOW) or ADCCON3 .0(SLOW) is set to 1, ADC enter Slow speed mode.