MS51
Nov. 28, 2019
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247
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Rev 1.00
MS51
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SE
RIES
TE
CHNICAL RE
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CE MA
N
UAL
Interrupt Latency
6.2.6.5
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction underway. Each interrupt flags are polled and priority decoded each
system clock cycle. If a request is active and all three previous conditions are met, then the hardware
generated LCALL is executed. This LCALL itself takes 4 clock cycles to be completed. Thus, there is a
minimum reaction time of 5 clock cycles between the interrupt flag being set and the interrupt service
routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last clock cycle of the instruction
being executed, then an additional delay is introduced. The maximum response time (if no other
interrupt is currently being serviced or the new interrupt is of greater priority) occurs if the device is
performing a RETI, and then executes a longest 6-clock-cycle instruction as the next instruction. From
the time an interrupt source is activated (not detected), the longest reaction time is 16 clock cycles.
This period includes 5 clock cycles to complete RETI, 6 clock cycles to complete the longest
instruction, 1 clock cycle to detect the interrupt, and 4 clock cycles to complete the hardware LCALL to
the interrupt vector location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 clock cycles
and not more than 16 clock cycles.
External Interrupt Pins
6.2.6.6
The external interrupt
INT0
̅̅̅̅̅̅̅
and
INT1
̅̅̅̅̅̅̅
can be used as interrupt sources. They are selectable to be
either edge or level triggered depending on bits IT0 (TCON.0) and IT1 (TCON.2). The bits IE0
(TCON.1) and IE1 (TCON.3) are the flags those are checked to generate the interrupt. In the edge
triggered mode, the
INT0
̅̅̅̅̅̅̅
or
INT1
̅̅̅̅̅̅̅
inputs are sampled every system clock cycle. If the sample is high in
one cycle and low in the next, then a high to low transition is detected and the interrupts request flag
IE0 or IE1 will be set. Since the external interrupts are sampled every system clock, they have to be
held high or low for at least one system clock cycle. The IE0 and IE1 are automatically cleared when
the interrupt service routine is called. If the level triggered mode is selected, then the requesting
source has to hold the pin low till the interrupt is serviced. The IE0 and IE1 will not be cleared by the
hardware on entering the service routine. In the level triggered mode, IE0 and IE1 follows the inverse
value of
INT0
̅̅̅̅̅̅̅
and
INT1
̅̅̅̅̅̅̅
pins. If interrupt pins continue to be held low even after the service routine is
completed, the processor will acknowledge another interrupt request from the same source. Both
INT0
̅̅̅̅̅̅̅
and
INT1
̅̅̅̅̅̅̅
can wake up the device from the Power-down mode.
