MS51
Nov. 28, 2019
Page
246
of 491
Rev 1.00
MS51
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SE
RIES
TE
CHNICAL RE
F
EREN
CE MA
N
UAL
EIPH2
– Extensive Interrupt Priority High 2
Register
SFR Address
Reset Value
EIPH2
CFH, Page 2
0000_0000 b
7
6
5
4
3
2
1
0
-
-
-
-
-
PUART4H
PUART3H
PUART2H
-
-
-
-
-
R/W
R/W
R/W
Bit
Name
Description
2
PUART4H UART4 interrupt priority high bit
1
PUART3H UART3 interrupt priority high bit
0
PUART2H UART2 interrupt priority high bit
Note:
EIPH2 is used in combination with the EIP2 to determine the priority of each interrupt source. See Table 6.2-4 Interrupt
Priority Level Setting for correct interrupt priority configuration.
Interrupt Service
6.2.6.4
The interrupt flags are sampled every system clock cycle. In the same cycle, the sampled interrupts
are polled and their priority is resolved. If certain conditions are met then the hardware will execute an
internally generated LCALL instruction, which will vector the process to the appropriate interrupt vector
address. The conditions for generating the LCALL are,
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last cycle of the instruction currently being executed.
3. The current instruction does not involve a write to any enabling or priority setting bits and is
not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every system clock cycle. If an interrupt flag is active in one cycle but not responded to for
the above conditions are not met, if the flag is not still active when the blocking condition is removed,
the denied interrupt will not be serviced. This means that the interrupt flag, which was once active but
not serviced is not remembered. Every polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate
service routine. This action may or may not clear the flag, which caused the interrupt according to
different interrupt source. The hardware LCALL behaves exactly like the software LCALL instruction.
This instruction saves the Program Counter contents onto the Stack RAM but does not save the
Program Status Word (PSW). The PC is reloaded with the vector address of that interrupt, which
caused the LCALL. Execution continues from the vectored address until an RETI instruction is
executed. On execution of the RETI instruction, the processor pops the Stack and loads the PC with
the contents at the top of the stack. User should take care that the status of the stack. The processor
does not notice anything if the stack contents are modified and will proceed with execution from the
address put back into PC. Note that a simple RET instruction would perform exactly the same process
as a RETI instruction, but it would not inform the Interrupt controller that the interrupt service routine is
completed. RET would leave the controller still thinking that the service routine is underway, making
future interrupts impossible.
