MS51
Nov. 28, 2019
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266
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Rev 1.00
MS51
32K
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CHNICAL RE
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memory map and does not share any on-chip peripherals.
When the OCDEN (CONFIG0.4) is programmed as 0 and LOCK (CONFIG0.1) remains un-
programmed as 1, the OCD is activated. The OCD cannot operate if chip is locked. The OCD system
uses a two-wire serial interface, ICE_DAT and ICE_CLK, to establish communication between the
target device and the controlling debugger host. ICE_DAT is an input/output pin for debug data
transfer and ICE_CLK is an input pin for synchronization with ICE_DAT data. The P2.0/nRESET pin is
also necessary for OCD mode entry and exit. The MS51 supports OCD with Flash Memory control
path by ICP writer mode, which shares the same three pins of OCD interface.
The MS51 uses ICE_DAT, ICE_CLK, and P2.0/nRESET pins to interface with the OCD system.
When designing a system where OCD will be used, the following restrictions must be considered for
correct operation:
1. If P2.0/nRESET is configured as external reset pin, it cannot be connected directly to V
DD
and
any external capacitors connected must be removed.
2. If P2.0/nRESET is configured as input pin P2.0, any external input source must be isolated.
3. All external reset sources must be disconnected.
4. Any external component connected on ICE_DAT and ICE_CLK must be isolated.
Limitation of OCD
6.3.3.2
The MS51 is a fully-featured microcontroller that multiplexes several functions on its limited I/O pins.
Some device functionality must be sacrificed to provide resources for OCD system. The OCD has the
following limitations:
1. The P2.0/nRESET pin needs to be used for OCD mode selection. Therefore, neither P2.0
input nor an external reset source can be emulated.
2. The ICE_DAT pin is physically located on the same pin P1.6. Therefore, neither its I/O
function nor shared multi-functions can be emulated.
3. The ICE_CLK pin is physically located on the same pin as P0.2. Therefore, neither its I/O
function nor shared multi-functions can be emulated.
4. When the system is in Idle or Power-down mode, it is invalid to perform any accesses
because parts of the device may not be clocked. A read access could return garbage or a
write access might not succeed.
5. HIRC cannot be turned off because OCD uses this clock to monitor its internal status. The
instruction that turns off HIRC affects nothing if executing under debug mode. When CPU
enters its Power-down mode under debug mode, HIRC keeps turning on.
The MS51 OCD system has another limitation that non-intrusive commands cannot be executed at
any time while the user’s program is running. Non-intrusive commands allow a user to read or write
MCU memory locations or access status and control registers with the debug controller. A reading or
writing memory or control register space is allowed only when MCU is under halt condition after a
matching of the hardware address breakpoint or a single step running.
