MS51
Nov. 28, 2019
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Input Capture Module
6.5.2.4
The input capture module along with Timer 2 implements the input capture function. The input capture
module is configured through CAPCON0~2 registers. The input capture module supports 3-channel
inputs (CAP0, CAP1, and CAP2). Each input channel consists its own noise filter, which is enabled via
setting ENF0~2 (CAPCON2[6:4]). It filters input glitches smaller than four system clock cycles. Input
capture channels has their own independent edge detector but share the unique Timer 2. Each trigger
edge detector is selected individually by setting corresponding bits in CAPCON1. It supports positive
edge capture, negative edge capture, or any edge capture. Each input capture channel has to set its
own enabling bit CAPEN0~2 (CAPCON0[6:4]) before use.
While input capture channel is enabled and the selected edge trigger occurs, the content of the free
running Timer 2 counter, TH2 and TL2, will be captured, transferred, and stored into the capture
registers CnH and CnL. The edge triggering also causes CAPFn (CAPCON0.n) set by hardware. The
interrupt will also generate if the ECAP (EIE0.2) and EA bit are both set. For three input capture flags
share the same interrupt vector, user should check CAPFn to confirm which channel comes the input
capture edge. These flags should be cleared by software.
The bit CAPCR (CAPCON2.3) benefits the implement of period calculation. Setting CAPCR makes the
hardware clear Timer 2 as 0000H automatically after the value of TH2 and TL2 have been captured
after an input capture edge event occurs. It eliminates the routine software overhead of writing 16-bit
counter or an arithmetic subtraction.
Control Registers of Timer 2
6.5.2.5
