NEC PG-FP4, Руководство пользователя

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User’s Manual U15260EJ3V1UM
101
CHAPTER 9 TARGET SYSTEM INTERFACE CIRCUITS
This chapter describes the target system interface circuits of the PG-FP4 (TTL level).
9.1 SO/TxD, RESET
For programming flash memory devices, V
DD
and V
DD2
may be supplied by the PG-FP4.
When V
DD
and V
DD2
are supplied by the target system, the PG-FP4 internal voltage regulator is protected so that
user V
DD
and V
DD2
will not affect the signal lines SO/TxD and RESET.
In either case, the signal lines SO/TxD and RESET will have TTL-level voltage.
Figure 9-1. SO/TxD and RESET Pins
Target system
V
DD2
generator
V
DD
generator
Signal
PG-FP4
1 k
Ω
74LV125
33
Ω