M-142 Multifunction Calibrator
MEATEST, s.r.o.
102
User Manual v54
RQS
Request Service, bit 6. The RQS bit is set to 1 whenever bits ESB or MAV change from 0 to 1 and are
enabled (1) in the SRE. When RQS is 1, the M142 asserts the SRQ control line on the IEEE-488
interface. You can do a serial poll to read this bit to see if the M142 is the source of an SRQ.
MSS
Master Summary Status, bit 6. The MSS bit is set to 1 whenever bits ESB or MAV are 1 and enabled
(1) in the SRE. This bit can be read using the *STB? command in serial remote control in place of doing
a serial poll.
ESB
Event Summary Bit, bit 5. The ESB bit is set to 1 when one or more enabled ESR bits are set to 1.
Conversely, the ESB bit is set to 0 when no enabled ESR bits are set to 1.
MAV
Message Available, bit 4. The MAV bit is set to 1 whenever data is available in the M142 IEEE488
Output Queue. This message is used to synchronize information exchange with the controller. The
controller can, for example, send a query command to the M142 and then wait for MAV to become
TRUE. The IEC 625-1 bus is available for other use while an application program is waiting for a
device to respond. If an application program begins a read operation of the Output Queue without first
checking for MAV, all system bus activity is held up until the M142 responds.
SRE Service Request Enable Register
The Service Request Enable Register is an 8-bit register that enables corresponding summary messages in the
Status Byte Register. Thus the application programmer can select reason for a device (M142) to issue a service
request by altering the contents of the SRE. The Service Request Enable Register is read with the *SRE?
common query. The response message to this query represents the sum of the binary-weighted values of the
SRE. The value of unused bit 6 shall always be zero. The Service Request Enable Register is written with the
*SRE common command followed by an integer value (0 – 191). Sending the *SRE common command
followed by a zero clears the SRE. A cleared register does not allow status information to generate a rsv local
message and thus, no service request are issued. The Service Request Enable Register is cleared upon power-on.
ESR Event Status Register
The Event Status Register is a two-byte register in which the higher eight bits are always 0, and the lower eight
bits represent various conditions of the M142 calibrator. The ESR is cleared when the power is turned on, and
every time it is read.
Bit configuration of Event Status Register :
PON
Power On, bit 7. This event bit indicates that an off-to-on transition has occurred in the device’s power
supply.
URQ
User Request, bit 6. This event bit indicates disconnecting or connecting of any cable adapter to the
auxiliary connector on the front panel.
CME
Command Error, bit 5. This event bit indicates that an incorrectly formed command or query has been
detected by the M142.
EXE
Execution Error, bit 4. This event bit indicates that the received command cannot be executed, owing to
the device state or the command parameter being out of bounds.
DDE
Device Dependent Error, bit 3. This event bit indicates that an error has occurred which is neither a
Command Error, a Query Error, nor an Execution Error. A Device-specific Error is any executed device
operation that did not properly complete due to some condition, such as overload.
QYE
Query Error, bit 2. This event bit indicates that either:
1. an attempt is being made to read data from the Output Queue when no output is either present or
pending
2. or data in the Output Queue has been lost
OPC
Operation Complete, bit 0. This event bit is generated in response to the *OPC command. It indicates
that the device has completed all selected pending operations.
