5.2.7 Status System Detail: Status Byte Register and Service Request (SRQ)
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The programming example in TABLE 5-4 initiates an SRQ when a command error is
detected by the instrument.
The programming example in Table 5-3 initiates an SRQ when a command error is
detected by the instrument.
Programming example to generate an SRQ
Command or operation
Description
*ESR?
Read and clear the Standard Event Status Register
*ESE 32
Enable the Command Error (CME) bit in the Standard Event Status Register
*SRE 32
Enable the Event Summary Bit (ESB) to set the RQS
*ABC
Send improper command to instrument to generate a command error
Monitor bus
Monitor the bus until the Service Request interrupt (SRQ) is sent
Initiate Serial Poll
Serial Poll the bus to determine which instrument sent the interrupt
and clear the RQS bit in the Status Byte
*ESR?
Read and clear the Standard Event Status Register allowing an SRQ to be
generated on another command error
5.2.7.4 Using Status Byte Query (*STB?)
The Status Byte Query (*STB?) command is similar to a Serial Poll except it is pro-
cessed like any other instrument command. The *STB? command returns the same
result as a Serial Poll except that the Status Byte bit 6 (RQS/MSS) is not cleared. In this
case bit 6 is considered the MSS bit. Using the *STB? command does not clear any bits
in the Status Byte Register.
5.2.7.5 Using Message Available (MAV) Bit
Status Byte summary bit 4 (MAV) indicates that data is available to read into your bus
controller. This message may be used to synchronize information exchange with the
bus controller. The bus controller can, for example, send a query command to the
Model 642 and then wait for MAV to set. If the MAV bit has been enabled to initiate an
SRQ, the user's program can direct the bus controller to look for the SRQ leaving the
bus available for other use. The MAV bit will be clear whenever the output buffer is
empty.
5.2.7.6 Using Operation Complete (*OPC) and Operation Complete Query (*OPC?)
The Operation Complete (*OPC) and Operation Complete Query (*OPC?) are both
used to indicate when pending device operations complete. However, the commands
operate with two distinct methods.
The *OPC command is used in conjunction with bit 0 (OPC) of the Standard Event Sta-
tus Register. If *OPC is sent as the last command in a command sequence, bit 0 will be
set when the instrument completes the operation that was initiated by the command
sequence. Additional commands may be sent between the instrument and the bus
controller while waiting for the initial pending operation to complete. A typical use of
this function would be to enable the OPC bit to generate an SRQ and include the *OPC
command when programming the instrument. The bus controller could then be
instructed to look for an SRQ allowing additional communication with the instru-
ment while the initial process executes.
TABLE 5-4
