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2-8
Functional Description
Notes:
When determining the update rate for a hardware pacer clock
(internal or external), make sure that you do not update the analog output
channels faster than the host computer writes to the input buffers of the
channels. Typical update rates range from 1kHz to 20kHz; the actual rate
depends on a number of factors, including your computer, the operating
system/environment, and software issues. Also keep in mind the settling
time of the channels on the DDA-08/16 board; refer to Appendix A for
information.
At power-up, the pacer clock is disabled.
Output Clock
If enabled, the output clock generates an output pulse for each update of
the analog output channels on the quad DACs in the update group (using
either the internal pacer clock or the external pacer clock). You can use
this output pulse to synchronize other devices to the pacer clock.
The output pulse is issued from the CLOCK OUT pin (pin 20) of the
main I/O connector. The polarity of the output pulse (falling edge or
rising edge) is software-selectable. If you select a falling-edge pulse, the
output from CLOCK OUT starts high; if you select a rising-edge pulse,
the output from CLOCK OUT starts low. On power-up, the board
assumes that you want to generate a falling-edge pulse.
Time Delay
Through software, you can specify a time delay between the update of the
analog output channels on the quad DACs in the update group and the
output clock pulse. The output clock determines the time delay by
multiplying the prescaler value used by the internal pacer clock by the
output clock’s own independent 8-bit counter value. The output clock
counter is reloaded each time the analog output channels are updated.
For example, if the prescaler value is 1ms and you want a 30ms time
delay between the update of the analog output channels and the output
clock pulse, the output clock counter value must be 30.
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