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2-6
Functional Description
Clocks
DDA-08/16 boards support two types of clocks: a pacer clock and an
output clock. These clocks are described in the following sections.
Pacer Clocks
The pacer clock determines the update rate (the time between each update
of all the channels on the quad DACs in the update group). DDA-08/16
boards provide the following software-selectable pacer clocks:
●
Hardware internal pacer clock
— The internal pacer clock uses an
onboard time base. The internal pacer clock determines the update
rate by multiplying a prescaler value (1
µ
s, 10
µ
s, 100
µ
s, 1ms, 10ms,
100ms, or 1s) by an 8-bit counter value. The prescaler values provide
a wide range of update rates; the 8-bit counter value provides the
resolution that allows you to achieve the exact update rate you
require.
The time between updates can range from 1
µ
s to 4.267 minutes.
For example, assume that you want to update the channels every
50ms. The prescaler value can be 1ms and the counter value can
be 50, or the prescaler value can be 10ms and the counter value can
be 5.
Notes:
The prescaler value used by the pacer clock is also used to
determine the length of the output clock pulse and the time delay between
the update of the analog output channels on the quad DACs in the update
group and the output clock pulse. Refer to page 2-8 for more information
about the output clock.
DriverLINX allows you to specify the Logical Channel (0 = Pacer Clock,
1 = Output Clock), Clock Source, Clock Tic Period, Mode, and Gate.
Refer to the
Using DriverLINX with Your Hardware, Keithley DDA-08/16
manual that accompanies your DriverLINX software.
When the pacer clock counter is loaded, the channels on the quad
DACs in the update group are updated and the pacer clock counter
starts counting down. (Note that a slight time delay occurs between
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