2-7
the time the pacer clock counter is loaded and the time the channels
are updated.) When the pacer clock counter counts down to zero, all
the channels on the quad DACs in the update group are updated again
and the process repeats.
●
Hardware external pacer clock
— An external pacer clock is useful
if you want to update the channels at rates not available with the
internal clock, if you want to update the channels at uneven intervals,
or if you want to update the channels based on an external event.
The external pacer clock is an externally applied TTL-compatible
signal, which you attach to the CLOCK IN pin (pin 1) of the main I/O
connector. At each active edge of the external pacer clock, the
channels are updated. The active edge is software-selectable; at
power-up, the board assumes that the active edge for an external pacer
clock is a falling edge.
Figure 2-2 illustrates how analog output channels are updated when using
an internal pacer clock and when using an external pacer clock with a
falling edge as the active edge. (Note that Figure 2-2 assumes that you are
not using a hardware trigger; refer to Figure 2-4 on page 2-12 when using
a hardware trigger.)
Figure 2-2. Using a Pacer Clock
Operation is started
Updates begin when
using an external
pacer clock
Updates begin when
using an internal
pacer clock
External Pacer
Clock
Internal Clock
Source
(idle state)
count
count
count
count
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