Intel Pentium III Processor 512K, Руководство по конструкции

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Design Guide 3
LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
Contents
1.0 Introduction
............................................................................................................................... 7
1.1 Related Documents .............................................................................................................. 7
1.2 Conventions and Terminology .............................................................................................. 8
2.0 General Design Considerations
........................................................................................ 9
2.1 Nominal Board Stackup ........................................................................................................ 9
2.2 Micro-FCBGA Component Keepout ................................................................................... 10
3.0 Processor Host Bus Design
.............................................................................................. 13
3.1 Initial Timing Analysis ......................................................................................................... 13
3.2 General Topology and Layout Guidelines .......................................................................... 14
3.3 Wired-OR Signal Considerations ........................................................................................ 15
3.4 Simulation Methodology ..................................................................................................... 16
3.5 Trace Routing ..................................................................................................................... 17
3.6 Layout Rules for AGTL Signals .......................................................................................... 17
3.6.1
Ground Reference ................................................................................................. 17
3.6.2 Reference Plane Splits .......................................................................................... 17
3.6.3 CPU Breakout ........................................................................................................ 17
3.6.4 Minimizing Crosstalk .............................................................................................. 17
3.7 Layout Rules for Non-AGTL (CMOS) Signals .................................................................... 18
3.8 Undershoot/Overshoot Requirements ................................................................................ 18
3.9 Debug Port Routing Guidelines .......................................................................................... 19
3.9.1
Target System Implementation .............................................................................. 19
4.0 Clocking
.................................................................................................................................... 24
4.1 General Clocking Considerations ....................................................................................... 24
4.2 Single Ended Host Bus Clocking Routing........................................................................... 25
4.2.1
CLKREF Filter Implementation .............................................................................. 27
4.2.2 Single-Ended Clocking BSEL[1:0] Implementation................................................ 28
4.3 Debug Port Host Clock Connection .................................................................................... 29
4.4 Clock Driver Decoupling and Power Delivery .....................................................................29
5.0 Power
.......................................................................................................................................... 30
5.1 Terminology ........................................................................................................................ 30
5.2 Typical Power Delivery ....................................................................................................... 30
5.3 LV Intel
®
Pentium
®
III Processor 512K Power Requirements ............................................32
5.3.1 Voltage Tolerance.................................................................................................. 32
5.3.2 Multiple Voltages ................................................................................................... 32
5.3.3 Voltage Sequencing...............................................................................................33
5.4 Meeting Dual Processor Power Requirements ................................................................... 33
5.4.1
Supplying Voltage .................................................................................................. 33
5.4.2 Decoupling Technology and Transient Response ................................................. 33
5.5 Recommendations .............................................................................................................. 35
5.5.1
Decoupling Guidelines for LV Intel
®
Pentium
®
III Processor 512K Designs ......... 35
5.5.2 PLL Filter Recommendations ................................................................................ 36