Intel Pentium III Processor 512K, Руководство по конструкции

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LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
Design Guide 25
4.2 Single Ended Host Bus Clocking Routing
LV Intel Pentium
III
processor 512K platforms support single-ended host bus clock drivers. When
using this clocking method, the BCLK signal (ball AC1) is used as the single-ended clock input to
the LV Intel Pentium
III
processor 512K. The BCLK#/CLKREF signal (ball AD1) is used as a
reference voltage and must be connected to the appropriate filter circuit described in “CLKREF
Filter Implementation” on page 27.
Figure 12 shows the topology that should be used for the LV Intel Pentium
III
processor 512K clock
traces. Please note that L0, L1, and L2 refer to trace lengths between the illustrated components.
Table 15 contains the recommended lengths and component values for this topology.
Figure 13 shows the topology that should be used for the chipset clock traces. Note that Ln refers to
trace lengths between the illustrated components. Table 15 contains the recommended lengths and
component values for this topology.
Figure 12. Single Ended Clocking Topology - CPU
Rs
+
–
L0 L1
Lclkref
Clock Driver
BCLK
CLKREF
Processor
CLKREF
Filter
Zo = 55
Ω
Zo = 55
Ω
Figure 13. Single Ended Clocking Topology
L0
L0
L0
L0
L1
L1
L2
L3
Processor 1
Processor 2
Chipset
PLL
R
S
R
S
R
S
R
S
Clock Driver