LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
38
Design Guide
6.0
Thermals
The LV Intel Pentium
III
processor 512K requires a robust thermal solution for proper operation.
Please refer to the Low Voltage Intel
®
Pentium
III
Processor 512K (DP) Thermal Design Guide for
more information.
6.1
THERMTRIP# Requirements
In the event the processor drives the THERMTRIP# signal active during valid operation, both the
Vcc and Vtt supplies to the processor must be powered off to prevent thermal runaway of the
processor. Valid operation refers to operating conditions in which the THERMTRIP# signal is
guaranteed valid. The time required from THERMTRIP# assertion to V
CC
rail at 1/2 nominal is
5 seconds; the time required from THERMTRIP# assertion to V
TT
rail at 1/2 nominal is 5 seconds.
6.2
THERMTRIP# Erratum
Intel has identified an issue with THERMTRIP# which may incorrectly assert during de-assertion
of RESET# at nominal operating temperatures in LV Intel Pentium
III
processor 512K A-1 stepping
processors. The assertion of THERMTRIP# with cause the processor to shut down internally and
stop execution. This issue can lead to intermittent system power-on boot failures.
To prevent the risk of power-on boot failures a platform workaround is required. The system must
provide a rising edge on the TCK signal during the power-on sequence that meets all of the
following requirements:
•
Edge occurs after Vcc
CORE
is valid and stable
•
Edge occurs before or at the de-assertion of RESET#
•
Edge occurs after all V
ref
input signals are at valid voltage levels
•
TCK input meets the Vih
min
and Vih
max
spec requirements of the Low Voltage Intel
®
Pentium
®
III
Processor 512K Datasheet.
Specific workaround implementations may be platform specific. The following example has been
tested as a acceptable workaround implementation.
The example workaround circuit, shown in Figure 23, requires circuit modifications for ITP tools
to function correctly. These modifications must remove the workaround circuitry from the platform
and may cause systems to fail to boot. Issuing the ITP ’Reset Target’ command on failing systems
will reset the system while providing a sufficient rising edge on the TCK pin to ensure system boot.
The example workaround circuit (shown in Figure 23) does not support production motherboard
test methodologies that require the use of the processor JTAG/TAP port. Alternative workaround
solutions must be found if such test capability is required.
Table 19. THERMTRIP# Timing Requirements
Power Rail
Power Target
Time Required for Power Drop
V
CC
1/2 Nominal V
CC
5.0 seconds
V
TT
1/2 Nominal V
TT
5.0 seconds
