LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
36
Design Guide
5.5.1.2
AGTL V
REF
Decoupling Design
Three 0.1-µF capacitors in 0603 packages should be placed within 500 mils of the V
REF
pins. Two
should be connected between V
TT
and V
REF
, and one should be connected between V
REF
and
ground. If this circuit is far from the processor, add a 0.1-µF capacitor for decoupling.
5.5.2
PLL Filter Recommendations
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL.
5.5.2.1
Topology
The LV Intel Pentium
III
processor 512K has internal phase lock loop (PLL) clock generators,
which are analog and require a quiet power supply to minimize jitter. PLL1 should have a 4.7-µH
inductor connected in series to V
TT
, and PLL2 should be connected through a capacitor (22- to
100-µF) to PLL1. See Figure 21.
Other routing requirements:
•
The capacitor (C) should be close to the PLL1 and PLL2 pins, < 0.1
Ω
per route.
•
The PLL2 route should be parallel and next to PLL1 route (minimize loop area).
•
The inductor (L) should be close to C; any routing resistance should be inserted between V
TT
and L.
Figure 21. Processor PLL Filter
PLL1
PLL2
Tualatin
Processor
22 -100 uF
4.7 uH
Vcc
CORE
V
TT
C
L
