LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
44
Design Guide
Table 25. Power Signals
CPU Pin
Pin Connection
TESTHI[2:1]
Connect individually to V
TT
through a 1 K
Ω
pull-up resistor.
TESTLO[2:1]
Connect to Ground through a 1 K
Ω
pull-down resistor.
PLL1, PLL2
Low pass filter on V
TT
provided on the system board. Typically a 4.7 µH inductor
in series with V
TT
is connected to PLL1 then through a series 22-100 µF
capacitor to PLL2.
Reserved
The following pins must be left as no-connects: A2, A5, A11, B1, C1, C22, D1,
D26, E1, F1, L5, N4, N24, P1, P4, P5, P26, AD4, AD13, AD23, AE8, AF17, AF18
Vcc
CORE
Connect to core voltage regulator. Provide low frequency decoupling.
Guidelines: Place twenty-four 0.22-µF X5R 0603 capacitors directly under the
package on the solder side of the motherboard using at least two vias per
capacitor node. Ten 10-µF X7R 6.3 V 1206-size ceramic capacitors should be
placed around the package periphery near the balls. Trace lengths to the vias
should be designed to minimize inductance. Avoid bending traces to minimize
ESL.
VREF[7:0]
Connect to Vref voltage divider made up of 75
Ω
1% and 150
Ω
1% resistors
connected to V
TT
. Processor VREF must be separate from Chipset VREF.
Guidelines: Three each (minimum) 0.1 µF in 0603 package placed within 500
mils of VREF pins.
VCMOS_REF
Use 75
Ω
/150
Ω
resistor divider network to create a 1.0 V V
CMOS_REF
value
derived from V
CC_CMOS
.
VTT_ PWRGOOD
Connected to V
TT
through a 1 K
Ω
pullup resistor, and connect to VttPWRGOOD
circuitry.
V
TT
Connect A26, C5, C7, C9, C11, C13, C15, C17, C19, C21, D5, E4, E6, G4, G23,
J4, J23, L4, L23, N23, R23, U23, V4, W23, AA4, AA23, AC4, AC23, AD6, AD8,
AD12, AD14, AD18, AD20, AE3, AE18, AF1, AF2 to 1.25 V regulator. Provide
high and low frequency decoupling.
Guidelines: Place ten 1-µF X7R 0603 ceramic capacitors close to the package.
Via and trace guidelines are the same as above.
