LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
10
Design Guide
Additional guidelines on board stack-up, placement, and layout include the following.
•
The board impedance (Z) should be between 49.5
Ω
and 60.5
Ω
(55
Ω
± 10% is
recommended).
•
The dielectric process variation in the PCB fabrication should be minimized.
•
The ground plane should not be split on the ground plane layer.
•
Keep vias for decoupling capacitors as close to the capacitor pads as possible.
2.2
Micro-FCBGA Component Keepout
Figure 2 shows the keepout zones and dimensions for the Micro-FCBGA package. Table 2
provides the values for the mechanical specifications.
Figure 2. Micro-FCBGA Component Keepout
35 (E)
35 (D)
PIN A1 CORNER
E1
D1
A
Ø 0.78 (b)
479 places
K2
SUBSTRATE KEEPOUT ZONE
DO NOT CONTACT PACKAGE
INSIDE THIS LINE
7 (K1)
8 places
5 (K)
4 places
NOTE: All dimensions in millimeters. Values shown are for reference only
A2
0.20
