LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
Design Guide
19
When performing simulations to determine impact of overshoot and undershoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the LV Intel Pentium
III
processor 512K performance, care must be
taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also
contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer
model will impact results and may yield excessive overshoot/undershoot.
Refer to the latest Low Voltage Intel
®
Pentium
®
III
Processor 512K Datasheet for detailed
undershoot/overshoot requirements.
3.9
Debug Port Routing Guidelines
This chapter describes the processor debug port, in-target probe (ITP) platform design guidelines.
3.9.1
Target System Implementation
Follow the implementation guidelines provided in this section to help ensure a fully functional ITP
debug system. These guidelines are preliminary, and additional changes may be required. The
signals involved in the ITP debug system are high speed signals and must be routed with high
speed design considerations in mind. The implementation offers flexibility in areas such as JTAG
routing (i.e., scan chain), addition of non-ITP compliant parts, and clock rate. However, the
implementation is not flexible in system and execution signal connections.
Intel uses an ITP for internal debug and system validation and recommends that all system designs
include a debug port.
3.9.1.1
Signal Layout Guidelines
The debug port (Test Access Port) is part of the processor scan chain. It must be connected to the
bus clock and system bus signals. This implies that the designer will place the Debug Port within
12 inches of the nearest processor.
There are three signal groups within the debug port, as described in the datasheet. Each group has a
different set of layout requirements. The system signals are special ITP-specific signals and are
both inputs and outputs. The JTAG signals are system resources and may be shared with local
JTAG tools. Input and output signals are available. The execution signals are a combination of
CMOS and AGTL level signals. They are both inputs and outputs to the ITP.
The ITP TCK and TMS signals must be routed with a maximum trace resistance of 2.0 ohm to
reduce the amount of DC shifting on these signals. This is due to the small termination values that
are recommended for these signals.
System Signal Layout Guidelines
Table 10 provides the system signal layout guidelines. See Table 13 for termination values.
