Intel Pentium III Processor 512K, Руководство по конструкции

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LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
Design Guide 21
Execution Signal Layout Guidelines
Figure 7. TCK Termination, DP System
Figure 3. TCK Termination, DP System
Table 12. Execution Signals Routing Guidelines
Signal Routing Notes Sample Layout
PREQx# AGTL signal routing guidelines apply Figure 6 (a)
PRDYx# Figure 8
RESET#
The flight time of the RESET# signal from the closest processor
must be added to the arrival time of BCLK at the Debug Port.
Figure 9
Figure 8. PRDYx# Signal Termination
Debug Port
Processor n
Rt
Termination Voltage
Rs