LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
28
Design Guide
4.2.2
Single-Ended Clocking BSEL[1:0] Implementation
In a LV Intel Pentium
III
processor 512K platform that uses single-ended (SE) clocking or a clock
source that does not support the VTT_PWRGD protocol, the normal BSEL frequency selection
process does not work. Since the clock generator is not compatible with dynamic BSEL assertions,
all BSEL[1:0] signals should not be connected together. Instead, the BSEL pins on the clock
generator should be pulled-up to 3.3 V through a 1 K
Ω
, 5% resistor. This strapping forces the clock
generator into 133 MHz clocking mode and will only support 133 MHz capable processors. In
addition, each BSEL[1:0] of each processor should be left unconnected. Figure 15 shows a diagram
of this implementation.
.
Figure 15. Single-Ended Clock BSEL Circuit (133 MHz)
Table 17. BSEL[1:0] Encoding
BSEL[1:0]
System Bus Frequency
11
133 MHz
NOTE: All other BSEL[1:0] combinations are not supported.
BSEL0
Processor 0
BSEL1
1K
W
5%
1K
W
5%
3.3V
3.3V
BSEL0
Clock Driver
BSEL1
BSEL0
Processor 1
BSEL1
NC
NC
NC
NC
