LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
14
Design Guide
Table 6 summarizes the flight time requirements for CPU to CPU transfers that result from using
the component timing specifications and recommended system timings. All component values
should be verified against the latest specifications before proceeding with analysis.
3.2
General Topology and Layout Guidelines
Intel recommends that all LV Intel Pentium
III
processor 512K dual-processing platforms use a
system bus T-topology. Figure 4 shows a high level diagram of this topology. The pull-up resistors
shown inside the processor packages are the processor’s on-die AGTL termination, since the LV
Intel Pentium
III
processor 512K has on-die termination.
Table 5. System Bus Timing Parameters
Timing Term
Value
T
skew
[ns]
0.25
T
jit
[ns]
0.20
T
adj
[ns]
0.50
T
cycle
[ns] (133 MHz)
7.50
Table 6. Sample CPU to CPU flight time calculations
Driver
Receiver
Calculation
CPU
CPU
T
flight,min
>= 1.0 - 0.4 + 0.25 = 0.85 ns
CPU
CPU
T
flight,max
<= 7.5 - 3.25 - 0.95 - 0.25 - 0.2 - 0.5 = 2.35 ns
Figure 4. System Bus T-Topology
Chipset
CPU0
CPU1
L0
L1
L2
RTTCTRL
V
TT
R1
R2
V
TT
R3
RTTCTRL
R4
