LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
26
Design Guide
The following guidelines should also be followed for single-ended clock implementations:
•
BCLK must be routed through trace impedance of 55
Ω
+/- 10%.
•
Use 4 mil wide traces.
•
Place all serial termination resistors within 0.50 inches to clock driver pins.
•
Place all other signals at least 20 mils from the clock traces.
•
All the termination resistors are rated at 1% accuracy.
•
Match processor 0 and processor 1 L1 lengths as close as possible (maximum delta of 0.20”)
Note:
The chipset may use a different clock reference level than the processor. This difference should be
considered when determining clock routing trace lengths.
Table 15. Component Values for SE Clocking Topology
Reference
Value
Notes
L0
0.25” to 0.5”
You may flood this area
L1
5” to 9”
Match processor 0 and processor 1 L1 lengths as close as
possible (maximum delta of 0.20”)
L2
L1 – 1.2”
L3
L1 – 0.6”
L3 length may be adjusted depending on the clock chip vendor
Lclkref
0” – 1”
Minimize this trace length
Rs
22 to 33
Ω
1% Tolerance
