Intel Pentium III Processor 512K, Руководство по конструкции

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LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
Design Guide 13
3.0 Processor Host Bus Design
3.1 Initial Timing Analysis
To determine the available flight time window, perform an initial timing analysis. Analysis of setup
and hold conditions will determine the minimum and maximum flight time bounds for the system
bus. Use the following equations to establish the system flight time limits.
Component timings for the LV Intel Pentium III processor 512K are available in the Low Voltage
Intel
®
Pentium
®
III Processor 512K Datasheet (order number 273673). Please contact your chipset
vendor for documentation concerning the chipset component timing.
Table 5 provides recommended values for system timings. Skew and jitter values for the clock
generator device come from the clock driver vendor’s datasheet. The PCB skew specification is
based on the results of extensive simulations performed by Intel engineers. The T
adj
value is based
on Intel’s experience with systems that use previous generations of processors.
Table 3. System Timing Equations
Equation
T
flight,min
>= T
hold
- T
co,min
+ T
skew
T
flight,max
<= T
cycle
- T
co,max
- T
su
- T
skew
- T
jit
- T
adj
Table 4. System Timing Terms
Term Description
T
cycle
System cycle time. Defined as the reciprocal of the frequency.
T
flight,min
Minimum system flight time.
T
flight,max
Maximum system flight time.
T
co,max
Maximum driver delay from input clock to output data.
T
co,min
Minimum driver delay from input clock to output data.
T
su
Minimum setup time. Defined as the time for which the input data must be valid prior to the
input clock.
T
hold
Minimum hold time. Defined as the time for which the input data must remain valid after the
input clock.
T
skew
Clock generator skew. Defined as the maximum delay variation between output clock
signals from the system clock generator, the maximum delay variation between clock
signals due to system board variation and chipset loading variation.
T
jit
Clock jitter. Defined as the maximum edge to edge variation in a given clock signal.
T
adj
Multi-bit timing adjustment factor. This term accounts for the additional delay that occurs in
the network when multiple data bits switch in the same cycle. The adjustment factor
includes mechanisms such as package and PCB crosstalk, high inductance current return
paths, and simultaneous switching noise.