Infineon C166S V1 SubSystem, Руководство пользователя

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User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
User’s Manual 11-6 V 1.6, 2001-08
CON.EN = 1: Operating Mode
LB 7 rw Loop Back Control
0
Normal output
1 Receive input is connected with transmit output
(half-duplex mode)
TEN 8 rw Transmit Error Enable
0
Ignore transmit errors
1 Check transmit errors
REN 9 rw Receive Error Enable
0
Ignore receive errors
1 Check receive errors
PEN 10 rw Phase Error Enable
0
Ignore phase errors
1 Check phase errors
BEN 11 rw Baudrate Error Enable
0
Ignore baudrate errors
1 Check baudrate errors
AREN 12 rw Automatic Reset Enable
0
No additional action upon a baudrate error
1 The SSC is automatically reset upon a baudrate
error
MS 14 rw Master Select
0
Slave Mode. Operate on shift clock received via
SCLK.
1 Master Mode. Generate shift clock and output it
via SCLK.
EN 15 rw Enable Bit = ‘0’
Transmission and reception disabled. Access to
control bits.
0 13 r Reserved; returns ‘0’ if read; should be written with ‘0’;
CON
Control Register
(Reset value: 0000
H
)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN MS 0 BSY BE PE RE TE
– – – –
BC
rw rw r rh rwh rwh rwh rwh r rw
Field Bits Type Description