Infineon C166S V1 SubSystem, Руководство пользователя

Страница: 114 / 460

User’s Manual
C166S V1 SubSystem
Central Processing Unit
User’s Manual 3-84 V 1.6, 2001-08
•
Controlling Interrupts
Software modifications (implicit or explicit) of the PSW are done in the execute phase of
instructions. In order to maintain fast interrupt responses, however, the current interrupt
prioritization round does not consider these changes, i.e., an interrupt request may be
acknowledged after the instruction that disables interrupts via IEN or ILVL, or after the
following instructions. Therefore, time-critical instruction sequences should not begin
directly after the instruction disabling interrupts, as shown in the following examples:
INTERRUPTS_OFF:
BCLR IEN ;globally disable interrupts
<Instr non-crit> ;non-critical instruction
<Instr 1st-crit> ;begin of uninterruptable critical sequence
. . .
<Instr last-crit> ;end of uninterruptable critical sequence
INTERRUPTS_ON:
BSET IEN ;globally re-enable interrupts
CRITICAL_SEQUENCE:
ATOMIC #3 ;immediately block interrupts
BCLR IEN ;globally disable interrupts
. . . ;here is the uninterruptable sequence
BSET IEN ;globally re-enable interrupts
Note: The described delay of 1 instruction also applies for enabling the interrupt system;
i.e., no interrupt requests are acknowledged until the instruction following the
enabling instruction.
•
External Memory Access Sequences
The effect described here will only become noticeable when watching the external
memory access sequences on the external bus (e.g., by means of a logic analyzer).
Different pipeline stages can simultaneously put a request on the External Bus Controller
(EBC). The sequence of instructions processed by the CPU may diverge from the
sequence of the corresponding external memory accesses performed by the EBC, due
to the predefined priority of external memory accesses:
1. Write data
2. Fetch code
3. Read data