Infineon C166S V1 SubSystem, Руководство пользователя

Страница: 399 / 460

User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
User’s Manual 11-9 V 1.6, 2001-08
Note: Only one SSC (etc.) can be master at a given time.
The transfer of serial data bits can be programmed in many respects:
– The data width can be specified from 2 bits to 16 bits
– A transfer may start with either the LSB or the MSB
– The shift clock may be idle low or idle high
– The data bits may be shifted with the leading edge or the trailing edge of the shift
clock signal
– The baudrate may be set from 457.76 Baud up to 30 MBaud (@ 60 MHz module
clock)
– The shift clock can be generated (MS_CLK) or can be received (SS_CLK)
These features allow the adaptation of the SSC to a wide range of applications in which
serial data transfer is required.
The Data Width Selection supports the transfer of frames of any data length, from 2-bit
“characters” up to 16-bit “characters”. Starting with the LSB (CON.HB=0) allows
communication with SSC devices in Synchronous Mode or with 8051 like serial
interfaces for example. Starting with the MSB (CON.HB=1) allows operation compatible
with the SPI interface.
Regardless of the data width selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right-aligned in registers TB and RB, with the LSB of the
transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the
internal shift register logic. The unselected bits of TB are ignored; the unselected bits of
RB will not be valid and should be ignored by the receiver service routine.
The Clock Control allows the adaptation of transmit and receive behavior of the SSC to
a variety of serial interfaces. A specific shift clock edge (rising or falling) is used to shift
out transmit data, while the other shift clock edge is used to latch in receive data. Bit
CON.PH selects the leading edge or the trailing edge for each function. Bit CON.PO
selects the level of the shift clock line in the idle state. Thus, for an idle-high clock, the
leading edge is a falling one, a 1-to-0 transition (see
Figure 11-4 ).
Field Bits Type Description
RB_VALUE [15:0] rh Receive Data Register Value
RB contains the received data value RB_VALUE.
Unselected bits of RB will be not valid and should be
ignored.