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User’s Manual

C166S V1 SubSystem

Central Processing Unit

User’s Manual

3-18

V 1.6, 2001-08

3.4

Interrupt and Exception Execution

An Interrupt and Exception Handler is responsible for managing all system and core
exceptions. There are four different kinds of exceptions that are executed in a similar
way:

• Interrupts generated by the InTerrupt Controller (ITC)
• DMA transfers issued by the Peripheral Event Controller (PEC).
• Software traps caused by the TRAP instruction
• Hardware traps issued by faults or specific system states

Normal Interrupt Processing

The CPU temporarily suspends the current program execution and branches to an
Interrupt Service Routine (ISR) in order to service an interrupt-requesting device. The
current program status [Instruction Pointer (IP), Processor Status Word (PSW), and in
segmentation mode, the Code Segment Pointer (CSP)] is saved on the internal system
stack. A prioritization scheme with 16 priority levels and with 4/8 sub-levels (4/8 group
levels) specifies the order of multiple interrupt-request handling. The maximum number
of interrupt requests is 112 (configured in steps of 16), wherein the lowest priority level
is reserved for the CPU and cannot be used for interrupts.

Software and Hardware Traps

Trap functions are activated in response to special conditions that occur during the
execution of instructions. A trap can also be caused externally by the Non-Maskable
Interrupt (NMI) pin. Several hardware trap functions are provided for handling erroneous
conditions and exceptions that arise during the program execution. Hardware traps
always have highest priority and cause immediate system reaction. The software trap
function is invoked by the TRAP instruction, which generates a software interrupt for a
specified interrupt vector. For all types of traps, the current program status is saved in
the system stack.

Interrupt Processing via the Peripheral Event Controller

A faster alternative to normal interrupt processing is servicing an interrupt requesting
device by the C166S's integrated PEC. Triggered by an interrupt request, the PEC
performs a single-word or byte data transfer between any two memory locations through
one of up to 16 programmable PEC service channels. During a PEC transfer, the normal
program execution of the CPU is halted. No internal program status information needs
to be saved. The same prioritization scheme is used for PEC service as for normal
interrupt processing.

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Содержание C166S V1 SubSystem

Страница 1: ...N e v e r s t o p t h i n k i n g Microcontrollers User s Manual V 1 6 August 2001 C166S V1 SubSystem C166S V1 SubS R1...

Страница 2: ...st Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list Warnings Due to technical requirements components may contain dangerous substances Fo...

Страница 3: ...Microcontrollers User s Manual V 1 6 August 2001 N e v e r s t o p t h i n k i n g C166S V1 SubSystem C166S V1 SubS R1...

Страница 4: ...Instruction description 6 78 RETI Instruction description 6 91 SRVWDT Instruction description 6 96 TRAP Instruction description 8 1 8 29 RP0H Register 8 1 8 34 DP3 P3 ODP4 ODP6 Registers 8 22 CLKEN S...

Страница 5: ...Purpose Timer Unit GPT12E 2 10 2 2 4 Parallel Ports PPorts 2 11 2 2 5 Periodic Wakeup from Idle or Sleep Mode 2 12 2 2 6 OCDS and JTAG 2 12 2 2 7 Core Control Block CCB 2 12 2 2 8 Clock Generation Un...

Страница 6: ...3 6 2 4 Indirect Addressing Modes 3 59 3 6 3 The System Stack 3 61 3 6 3 1 Stack Overflow and Underflow 3 62 3 6 3 2 Linear Stack 3 64 3 6 3 3 Circular Virtual Stack 3 65 3 7 Data Processing 3 68 3 7...

Страница 7: ...et 5 1 5 1 Short Instruction Summary 5 1 5 2 Instruction Set Summary 5 3 5 3 Instruction Opcodes 5 16 5 4 Instruction Description 5 21 6 Detailed Instruction Set 6 1 7 Parallel Ports 7 1 7 1 Alternate...

Страница 8: ...s Reception 10 15 10 3 2 3 Synchronous Timing 10 15 10 3 3 Baudrate Generation 10 17 10 3 3 1 Baudrate in Asynchronous Mode 10 17 10 3 3 2 Baudrate in Synchronous Mode 10 21 10 3 4 Hardware Error Dete...

Страница 9: ...User s Manual C166S V1 SubSystem Table of Contents Page User s Manual I 5 V 1 6 2001 08 12 3 2 Auxiliary Timer T5 12 34 12 3 3 Timer Concatenation 12 38 13 Instruction Index 13 1 14 Keyword Index 14 1...

Страница 10: ...User s Manual C166S V1 SubSystem User s Manual I 6 V 1 6 2001 08...

Страница 11: ...a defined maximum response time Embedded control applications also are often sensitive to board space power consumption and overall system cost Embedded control applications therefore require microco...

Страница 12: ...n to the standard on chip peripherals in order to build application specific derivatives As programs for embedded control applications become larger high level languages are favoured by programmers be...

Страница 13: ...e support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Efficiency Bit byte and word data types Flexible and efficient addressing modes for high code den...

Страница 14: ...pt lines General Purpose Timer Unit Timer Block 2 fPDBUS 2 maximum resolution 2 independent timers counters Timer counters can be concatenated 3 operation modes timer gated timer counter Extendend cap...

Страница 15: ...n circuit emulators Infineon incorporates its strategic tool partners very early into the product development process making sure embedded system developers get reliable well tuned tool solutions whic...

Страница 16: ...User s Manual C166S V1 SubSystem Introduction User s Manual 1 6 V 1 6 2001 08...

Страница 17: ...the Internal Bus Interface an internal representation of the external bus interface This bus provides a standardized method of integrating application specific peripherals to produce derivatives of t...

Страница 18: ...t of the C166S s instructions can be executed in just one machine cycle which requires 2 CPU clock cycles T1 and T2 2 1 ICPU 4 TCL For example shift and rotate instructions are always processed within...

Страница 19: ...pipeline has been filled one instruction is completed per machine cycle except for multiply and divide An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bit...

Страница 20: ...irst iteration of a loop Thus only one additional machine cycle is lost during the execution of the entire loop In loops which fall through upon completion no additional machine cycles is lost when ex...

Страница 21: ...ot frequently used This decreases the instruction decode time while also simplifying the development of compilers and assemblers 3 Provide most frequently used instructions with one word instruction f...

Страница 22: ...only be interrupted by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vector location 3 Multiple Register Banks This feat...

Страница 23: ...e number of register banks is only restricted by the available DPRAM space For easy parameter passing a register bank may overlap others A system stack is provided as a storage for temporary data The...

Страница 24: ...ies In addition different address ranges may be accessed with different bus characteristics Up to 5 external CS signals can be generated in order to save external glue logic Access to very slow memori...

Страница 25: ...urpose IO pin Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock ICPU The on chip oscillator derives the CPU clock from the crystal or from the external clock signal...

Страница 26: ...C0 transmits or receives characters of 2 16 bits length synchronously to a shift clock which can be generated by the SSC0 master mode or by an external master slave mode The SSC0 can start shifting wi...

Страница 27: ...gisters The output driver is disabled when an I O line is configured as input This allows true bidirectional ports which are switched to high impedance state when configured as inputs Further features...

Страница 28: ...efore make on IP events only simple monitor mode or JTAG based debugging through instruction injection The C166S OCDS is controlled by the debugger1 through a set of registers accessible from the JTAG...

Страница 29: ...al bus clock is limited to 50 MHz For not limiting the core to this frequency the peripherals are decoupled from the CPU by their own clock domain The frequency of the peripheral clock domain is eithe...

Страница 30: ...serviced by the application software the high byte of the Watchdog Timer is reloaded Thus time intervals between 10 s and 336 ms default after reset can be monitored referred to a PDBUS clock of 50 M...

Страница 31: ...C166S has 5 main units that are listed below All these units have been optimized to achieve maximum performance and flexibility High Performance Instruction Fetch Unit IFU High bandwidth fetch interfa...

Страница 32: ...2001 08 4 stage execution pipeline 7 Address and Data Unit ADU 16 bit arithmetic unit for address generation 8 Arithmetic and Logic Unit ALU 8 bit and 16 bit arithmetic unit 16 bit barrel shifter Mul...

Страница 33: ...me of this register bitX Name of bit bitfieldX Name of bitfield A16 A8 Long 16 bit address Short 8 bit address SFR ESFR Register space SFR or ESFR Register Register contents after reset 0 1 defined va...

Страница 34: ...Y defined by reset configuration n n bit number of bit m n n bit number of first bit of the bitfield m bit number of last bit of the bitfield type r readable by software w writable by software h writ...

Страница 35: ...sters can be modified explicitly by the programmer and implicitly by the CPU during normal instruction processing Note Note that any explicit write request via software to a C SFR supersedes a simulta...

Страница 36: ...DH to write to any number of bits in either byte of an SFR without disturbing the non addressed byte and the unselected bits Reserved Bits Some of the bits which are contained in the C166S s SFRs are...

Страница 37: ...nd the segment of jump or call instructions can be specified by several addressing modes The IP register may be updated using relative absolute or indirect modes The CSP register can be updated only b...

Страница 38: ...GPR must always contain a 0 or a hardware trap would occur seg Specifies an absolute code segment number The C166S supports 256 differ ent code segments so only the 8 lower bits respectively of the se...

Страница 39: ...time of a sequential and non sequential instruction flow is mainly given by the instruction fetch from different kind of memories number of waitstates The following pipeline diagram Table 3 2 shows t...

Страница 40: ...Table 3 3 Unconditional branches LM Bus 0 1 waitstate Clock Cycle T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 LM Address Ia_t LM Data 32bit Id_t Id_t FETCH In In 1 branch It It 1 It 2 DECODE In 1 In In 1 bra...

Страница 41: ...fetched After each subsequent execution of the same cache jump instruction the jump target instruction is not fetched from program memory but taken from the cache and immediately injected into the fet...

Страница 42: ...local memory 0 1 waitstates Table 3 6 Conditional cached branches LM Bus 0 1 waitstate Clock Cycle T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 Address Ia_t 1 Data 32bit Id_t 1 Id_t 1 FETCH In In 1 branch In 2...

Страница 43: ...additional NOP instructions are required All instructions requiring multiple cycles or hold states for execution are considered as one instruction ATOMIC and EXTended instructions can be used with an...

Страница 44: ...dedicated 24 bit code address pointer is used to access the memories for instruction fetches This pointer has two parts An 8 bit Code Segment Pointer CSP and a 16 bit offset Instruction Pointer IP The...

Страница 45: ...to access instructions The lower 8 bits of register CSP select one of up 256 segments of 64 KBytes each while the higher 8 bits are reserved for future use IP Instruction Pointer H H Reset value 0000H...

Страница 46: ...r is automatically loaded with the segment address of the vector location Non Segmented Mode In the non segmented mode the CSP is fixed to segment 0 It is no longer possible to modify the CSP either d...

Страница 47: ...5 SYS CON4 SYS CON3 SYS CON2 SYS CON1 SYS CON0 rw rw rw rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description SYSCON0 SYSCON9 0 9 rwh SYStem CONfiguration ROMEN 10 rwh Internal ROM E...

Страница 48: ...the lowest priority level is reserved for the CPU and cannot be used for interrupts Software and Hardware Traps Trap functions are activated in response to special conditions that occur during the ex...

Страница 49: ...e corresponding action which depends on the required functionality normal interrupt PEC etc of the arbitration winner An action request will be accepted by the CPU if the requesting source has a highe...

Страница 50: ...programmed for each interrupt request line by the 2 bit bitfield GLVL and the group extension bit xxGP of the register xxIC Note All interrupt request sources that are enabled and programmed to the s...

Страница 51: ...atus information of the associated source which is required during one round of prioritization arbitration cycle The upper 8 bits of the respective register are reserved All interrupt control register...

Страница 52: ...jump table that is located in the C166S s address space The jump table contains the appropriate jump instructions that transfer control to the interrupt or trap service routines These routines may be...

Страница 53: ...y i e 15 Therefore no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed The TRAP instruction does not change the CPU level so software trap service rou...

Страница 54: ...rity field ILVL in PSW is updated with the priority of the interrupt request that is to be serviced so the CPU now executes on the new level After accepting an interrupt request the C166S sends an ack...

Страница 55: ...mmediate value New_Bank The new CP value sets a new register bank The service routine may now use its own registers This register bank is preserved when the service routine is terminated i e its conte...

Страница 56: ...iggered by a real hardware event 3 4 5 2 Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime not identified at assembly time The C166S distinguishes...

Страница 57: ...1 TFR Trap Flag Register SFR FFACH D6H Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NMI STK OF STK UF 0 0 0 0 0 UND OPC 0 0 0 PRT FLT ILL OPA ILL INA ILL BUS rwh rwh rwh r r r r r rwh r r...

Страница 58: ...trap can interrupt a Class B trap The Debug trap is a special kind of interrupt service channel for debug purposes whose priority lies between the Class A trap and the reset function This allows the d...

Страница 59: ...s A traps occur simultaneously both trap flags are set The trap with the higher priority is executed After return from the service routine the IP is popped from the stack and immediately pushed again...

Страница 60: ...he SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an add instruction...

Страница 61: ...ected instructions Whenever one protected instruction is executed and the protection is broken the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine The IP value...

Страница 62: ...two memory locations is to be performed During a PEC transfer the normal program execution of the CPU is halted for just 1 machine cycles No internal program status information needs to be saved The P...

Страница 63: ...PEC address pointers segment offset can be modified incremented by the PEC transfer mechanism The highest 8 bits which represent the segment number are not modified by hardware Therefore the PEC poin...

Страница 64: ...annel x Source Address bits 15 0 DSTPx PEC Destination Pointer DPRAM H H Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSTPx rwh Field Bits Type Description DSTPx 15 0 rwh Destination Pointe...

Страница 65: ...ment Pointer SFR H H Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSTSNx SRCSNx rw rw Field Bits Type Description DSTSNx 15 8 rw Destination Pointer Segment Address of Channel x Destination...

Страница 66: ...n PT 15 rw Transfer Mode1 0 Short Transfer Mode 1 Long Transfer Mode EOPINT 14 rw End of PEC Interrupt Selection2 0 EOP interrupt with the same level as the PEC transfer is triggered 1 EOP interrupt i...

Страница 67: ...er the PEC transfer If the pointers are not to be modified INC 00B the respective channel will always move data from the same source to the same destination BWT 8 rw Byte Word Transfer Selection 0 Tra...

Страница 68: ...COUNT is not decremented by the transfers and the respective PEC channel can serve unlimited number of PEC requests until it is modified by the program c If the bitfield COUNT is set to service a spe...

Страница 69: ...nter permits servicing up to 65536 byte transfers or up to 32768 word transfers a If the PEC transfer counter COUNT2 value is set to 0000H the normal interrupt requests are processed instead of PEC da...

Страница 70: ...INT is set to 1 If EOPINT is 0 the request flag will not be cleared and another interrupt request will be generated on the same priority level The respective PEC channel remains idle and the associate...

Страница 71: ...rred the PEC service request processing is automatically switched to the other PEC channel of the pair CL of the previously active PEC channel is then reset Every channel toggle is indicated to CPU by...

Страница 72: ...e interrupt control register whereby in this IC register only the even numbered PEC channel is indicated with the priority group bits Table 3 8 PEC Channels That Can Be Linked Together Linked PEC Chan...

Страница 73: ...rity level PEC channel x x 3 x 2 x 1 x 0 linked to Interrupt priority level 1 PLEV 1 PLEV 0 x 2 Group priority level x 3 x 1 x 0 3 1 The following table lists all possible combinations All interrupt r...

Страница 74: ...rol bit EOPINT is set to 1 in the corresponding PECCx EOPIC Interrupt Control Register bSFR xxxxH xxH 1 Reset value 0000H 1 The EOPIC register is assigned to one of the 64 interrupt control registers...

Страница 75: ...2 0 No special EOP interrupt request is pending for PEC channel x 1 PEC channel x has raised an EOP interrupt request CxIE 14 12 10 8 6 4 2 0 rw Interrupt Sub Node Enable Control Bit of PEC Channel x...

Страница 76: ...y selected bank The C166S can switch the complete GPR bank with a single instruction for time critical tasks After switching the new task is executed within its own separate context There are 3 differ...

Страница 77: ...ificant bits are ignored The physical GPR address is calculated in a similar fashion as the short 4 bit GPR addresses For single bit GPR accesses the GPR s word address is calculated in the same way T...

Страница 78: ...3H 3H General Purpose word Register R3 UUUUH R4 CP 8 F4H 4H General Purpose word Register R4 UUUUH R5 CP 10 F5H 5H General Purpose word Register R5 UUUUH R6 CP 12 F6H 6H General Purpose word Register...

Страница 79: ...ose byte Register RL3 UUH RL2 CP 4 F4H 4H General Purpose byte Register RL4 UUH RH2 CP 5 F5H 5H General Purpose byte Register RL5 UUH RL3 CP 6 F6H 6H General Purpose byte Register RL6 UUH RH3 CP 7 F7H...

Страница 80: ...It is the user s responsibility to ensure that the physical GPR address specified via CP register plus short GPR address must always be an RAM location If this condition is not met unexpected results...

Страница 81: ...k pushes the value of the current context pointer CP into the system stack and loads CP with the immediate value New_Bank which selects a new register bank The service routine may now use its own regi...

Страница 82: ...ect access to any GPR in the currently active context Both Rw and Rb require 4 bits in the instruction format The base address of the global register bank is determined by the contents of register CP...

Страница 83: ...proc ess described for the Rb and Rw addressing modes bitoff Specifies direct access to any word in the bit addressable memory space The bitoff value requires 8 bits in the instruction format Dependin...

Страница 84: ...have different meanings Bits 13 0 specify a 14 bit data page offset while bits 15 14 specify the Data Page Pointer DPP 1 of 4 register which is used to generate the full 24 bit address see figure belo...

Страница 85: ...EXTended instructions and PEC data transfers Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit address with the contents of the DDP register selected by...

Страница 86: ...struction updating the DPPx register DPP0 Data Page Pointer 0 SFR FE00H 00H Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 DPP0PN r r r r r r rw DPP1 Data Page Pointer 1 SFR FE02H...

Страница 87: ...hanism Instruction EXTP R replaces the contents of the DPP register while instruction EXTS R concatenates the complete 16 bit long address with the specified segment base address The overriding page o...

Страница 88: ...pecifies the data page offset and the DPP The long addressing mode is referred to by the mnemonic mem Note The long addressing mode may be used with the DPP overriding mechanism EXTP R and EXTS R Tabl...

Страница 89: ...ructions use only the lowest 4 word GPRs R3 R0 as indirect address pointers which are then specified via short 2 bit addresses Physical addresses are generated from indirect address pointers using the...

Страница 90: ...15 R0 as indirect address pointer Some instructions accept only the lower four GPRs R3 R0 Rw The specified indirect address pointer is automatically post incremented by 2 or 1 for word or byte data op...

Страница 91: ...he non bit addressable Stack Pointer SP register is used to point to the Top Of the System TOS stack The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incr...

Страница 92: ...rflow and stack overflow traps to cache portions of a larger external stack Only the portion of the system stack currently being used is placed into the internal memory thus allowing a greater portion...

Страница 93: ...a stack overflow condition is detected just during entry into an ISR or during an ATOMIC EXTend sequence Under these conditions additional stack word locations are required to push IP PSW and CSP for...

Страница 94: ...via MOV instructions or the limits of the stack area STKOV STKUN are changed so that SP is outside the new limits 3 6 3 2 Linear Stack The C166S offers a linear stack option STKSZ 111B in which the s...

Страница 95: ...this technique should not be used because of the overhead of flushing and filling The basic mechanism is the transformation of the addresses of a virtual stack area controlled via SP STKOV and STKUN t...

Страница 96: ...selected maximum stack size The next instruction will push register R2 onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV SP 0F802H Se...

Страница 97: ...he transfer is complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits O...

Страница 98: ...selectable branch test The status flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine 3 7 1 Data Types The C166S supports operations on boolean bit bit stri...

Страница 99: ...ted unsigned long 4 0 to 4294967295UL Not directly supported float 4 1 176E 38 to 3 402E 38 Not directly supported double 8 2 225E 308 to 1 797E 308 Not directly supported long double 8 2 225E 308 to...

Страница 100: ...on A 16 bit barrel shifter provides multiple bit shifts in a single machine cycle Rotations and arithmetic shifts are also supported 3 7 4 Bit manipulation Unit The C166S offers a large number of inst...

Страница 101: ...text pointer CP Even GPRs which are allocated to not bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware effected bits In these cases the ha...

Страница 102: ...ts the 16 bit remainder Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control MDC register is set to 1 When a multiplication or d...

Страница 103: ...o avoid erroneous results The Multiply Divide Control Register MDC The bit addressable 16 bit Multiply Divide Control register is implicitly used by the CPU when it performs a multiplication or a divi...

Страница 104: ...The result is then stored in register MD The overflow flag V is set if the result of a multiply or divide instruction is greater than 16 bits This flag can be used to determine whether both word halv...

Страница 105: ...ecified only the low portion of MD must be loaded The result is also stored in MD The low portion MDL contains the integer result of the division while the high portion MDH contains the remainder The...

Страница 106: ...E Z V C N rwh rw rw r r r rw rwh rwh rwh rwh rwh rwh Field Bits Type Description ILVL 15 12 rwh CPU Priority LeVeL 0H Lowest priority FH Highest priority IEN 11 rw Interrupt PEC ENable Bit globally 0...

Страница 107: ...data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit operations with two operands the N flag represents the logical...

Страница 108: ...estimated as up to one half of the LSB of the result In conjunction with the V flag the C flag allows the rounding error to be evaluated with a finer resolution see table below For Boolean bit operat...

Страница 109: ...cuted This normally means that the MULIP flag is cleared again after that Note The MULIP flag is a part of the task environment When the ISR does not return to the interrupted multiply divide instruct...

Страница 110: ...ing the execute stage of the instruction 4th WRITE BACK In this stage all external operands and the remaining operands within the DPRAM space are written back A particularity of the C166S are the so c...

Страница 111: ...e while write is finished So the effect of this operation will not be seen immediately within next instruction After writing to a memory location MEMLOC non critical instruction s must follow before t...

Страница 112: ...P value that is to be updated by the preceding instruction Thus to make sure that the new CP value is used at least two instructions must be inserted between an instruction that changes the CP and a s...

Страница 113: ...ely preceding instructions Thus in order to use the new SP register value without erroneously performed stack accesses at least two instructions must be inserted between an instruction that explicitly...

Страница 114: ...last crit end of uninterruptable critical sequence INTERRUPTS_ON BSET IEN globally re enable interrupts CRITICAL_SEQUENCE ATOMIC 3 immediately block interrupts BCLR IEN globally disable interrupts he...

Страница 115: ...System Configuration The instruction following an instruction that changes the system configuration via register SYSCON e g the mapping of the internal local memory segmentation stack size cannot use...

Страница 116: ...Rs such as peripheral control registers which have effect over the system behavior for example enabling disabling transfer interrupts etc To assure that the critical write operation has been completed...

Страница 117: ...parallel with the CPU This section summarizes execution times The table below shows the minimum execution times required to process an instruction fetched from the internal local memory the DPRAM or e...

Страница 118: ...instruction Internal Local Memory operand accesses same for byte and word operand accesses DPRAM operand reads via indirect addressing modes Internal SFR operand reads immediately after writing Extern...

Страница 119: ...sable register are fixed at 1 by hardware This register is read only Register ONES can be used as a register addressable constant of all ones for bit manipulation or mask generation It can be accessed...

Страница 120: ...evision number of the implemented C166S module CPUID CPU Identification Register ESFR F00CH E 06H Reset value 04 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPUREVNO CPUMODNO r r Field Bits Type Descripti...

Страница 121: ...iting to a GPR byte does not affect another byte of the GPR Table 3 21 Addressing modes to access Word GPRs Name Physical Address 8 Bit Address 4 Bit Address Description Reset Value R0 CP 0 F0H 0H Gen...

Страница 122: ...egister RL3 UUH RL2 CP 4 F4H 4H General Purpose byte Register RL4 UUH RH2 CP 5 F5H 5H General Purpose byte Register RL5 UUH RL3 CP 6 F6H 6H General Purpose byte Register RL6 UUH RH3 CP 7 F7H 7H Genera...

Страница 123: ...ot directly writable 0000H DPP0 FE00H 00H Data Page Pointer 0 10 bits 0000H DPP1 FE02H 01H Data Page Pointer 1 10 bits 0001H DPP2 FE04H 02H Data Page Pointer 2 10 bits 0002H DPP3 FE06H 03H Data Page P...

Страница 124: ...FE02H 01H Data Page Pointer 1 10 bits 0001H DPP2 FE04H 02H Data Page Pointer 2 10 bits 0002H DPP3 FE06H 03H Data Page Pointer 3 10 bits 0003H CSP FE08H 04H Code Segment Pointer 8 bits not directly wri...

Страница 125: ...r 8 Segment Address Reg PEC Pointer PECSN 1 PEC Pointer Segment Address Reg PEC Pointer PECSN151 PEC Pointer 15 Segment Address Reg PEC Pointer PECC0 PEC Channel 0 Control Register PEC Control PECC PE...

Страница 126: ...User s Manual C166S V1 SubSystem Central Processing Unit User s Manual 3 96 V 1 6 2001 08...

Страница 127: ...ster SFR and Extended Special Function Register ESFR areas and external memory are mapped into one common address space Figure 4 1 C166S Address Space Overview 254 129 255 00 0000H 0 127 128 64 4 3 2...

Страница 128: ...FFH are the SFRs and ESFRs and the DPRAM areas The lower 32 KByte of segment 0 00 0000H 00 7FFFH may be occupied by a part of the on chip program memory and is called the internal Local Memory LM area...

Страница 129: ...t lower addresses The byte ordering is illustrated in Figure 4 2 Bit position 0 is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the...

Страница 130: ...ng option only for the internal LM area Devices with an LM size above 32 KByte expand the LM area from the middle of segment 1 i e starting at address 01 8000H The internal LM can be used for both cod...

Страница 131: ...Any word data access is made on an even byte address The highest possible word data storage location in the DPRAM is 00 FDFEH The highest possible code storage location in the DPRAM is either 00 FDFEH...

Страница 132: ...GPRs are not mapped into the SFR and ESFR memory area Using the corresponding long address instead of a GPR access executes an internal peripheral bus access The upper half of each register block is...

Страница 133: ...r initialization and mode selection Registers that need to be accessed frequently are allocated to the standard SFR area wherever possible Note The tools are equipped to monitor accesses to the ESFR a...

Страница 134: ...atile and non volatile memories The external bus interface may further limit the amount of addressable off chip memory The internal bus interface provides an internal system bus that allows the on chi...

Страница 135: ...dary crossing is not supported and may lead to erroneous results Segments are contiguous 64 KByte blocks They are referenced via the Code Segment Pointer CSP for code fetches and via an explicit segme...

Страница 136: ...ainst data destruction but also to implement a circular stack with hardware supported system stack flushing and filling except for option STKSZ 111 4 6 1 Data Organization in General Purpose Registers...

Страница 137: ...ing a new active register bank is simply done by updating the CP register Figure 4 4 Mapping of General Purpose Registers to DPRAM Addresses A particular Switch ConteXT SCXT instruction performs regis...

Страница 138: ...ot use F00AH reserved ESFR 05H reserved do not use F00CH CPUID ESFR 06H CPU Identification Register 0410H F00EH reserved ESFR 07H reserved do not use F010H reserved ESFR 08H reserved do not use F012H...

Страница 139: ...20H F042H ESFR 21H F044H ESFR 22H F046H ESFR 23H F048H ESFR 24H F04AH ESFR 25H F04CH ESFR 26H F04EH ESFR 27H F050H ESFR 28H F052H ESFR 29H F054H ESFR 2AH F056H ESFR 2BH F058H ESFR 2CH F05AH ESFR 2DH...

Страница 140: ...7H F070H ESFR 38H F072H ESFR 39H F074H ESFR 3AH F076H ESFR 3BH F078H ESFR 3CH F07AH ESFR 3DH F07CH ESFR 3EH F07EH ESFR 3FH F080H ESFR 40H F082H ESFR 41H F084H ESFR 42H F086H ESFR 43H F088H ESFR 44H F0...

Страница 141: ...00H F0BAH IRQ97IC ESFR 5DH IRQ97 Interrupt Control Register 0000H F0BCH IRQ98IC ESFR 5EH IRQ98 Interrupt Control Register 0000H F0BEH IRQ99IC ESFR 5FH IRQ99 Interrupt Control Register 0000H F0C0H IRQ1...

Страница 142: ...BH IRQ111 Interrupt Control Register 0000H F0D8H DTIDR ESFR 6CH Task ID register 0000H F0DAH ESFR 6DH F0DCH ESFR 6EH F0DEH ESFR 6FH F0E0H ESFR 70H F0E2H ESFR 71H F0E4H ESFR 72H F0E6H ESFR 73H F0E8H ES...

Страница 143: ...85H reserved do not use F10CH reserved ESFR b 86H reserved do not use F10EH reserved ESFR b 87H reserved do not use F110H reserved ESFR b 88H reserved do not use F112H reserved ESFR b 89H reserved do...

Страница 144: ...FR b A1H IRQ81 Interrupt Control Register 0000H F144H IRQ82IC ESFR b A2H IRQ82 Interrupt Control Register 0000H F146H IRQ83IC ESFR b A3H IRQ83 Interrupt Control Register 0000H F148H IRQ84IC ESFR b A4H...

Страница 145: ...ter 0000H F17CH IRQ41IC ESFR b BEH IRQ41 Interrupt Control Register 0000H F17EH IRQ15IC ESFR b BFH IRQ15 Interrupt Control Register 0000H F180H EOPIC ESFR b C0H End of PEC Transfer Interrupt Control R...

Страница 146: ...F1A4H ESFR b D2H F1A6H ESFR b D3H F1A8H ESFR b D4H F1AAH ESFR b D5H F1ACH ESFR b D6H F1AEH ESFR b D7H F1B0H ESFR b D8H F1B2H ESFR b D9H F1B4H ESFR b DAH F1B6H ASC0PISEL ESFR b DBH ASC0 Port Input Sele...

Страница 147: ...reserved do not use F1ECH reserved reserved do not use F1EEH reserved reserved do not use F1F0H reserved reserved do not use F1F2H reserved reserved do not use F1F4H reserved reserved do not use F1F6...

Страница 148: ...text Pointer Register FC00H FE12H SP SFR 09H CPU System Stack Pointer Register FC00H FE14H STKOV SFR 0AH CPU Stack Overflow Pointer Register FA00H FE16H STKUN SFR 0BH CPU Stack Underflow Pointer Regis...

Страница 149: ...er 0000H FE48H T6 SFR 24H GPT Timer 6 Register 0000H FE4AH CAPREL SFR 25H GPT Capture Reload Register 0000H FE4CH GPTIPISEL SFR 26H GPT Port Input Selection Register 0000H FE4EH SFR 27H FE50H SFR 28H...

Страница 150: ...DH FE7CH SFR 3EH FE7EH SFR 3FH FE80H SFR 40H FE82H SFR 41H FE84H SFR 42H FE86H SFR 43H FE88H SFR 44H FE8AH SFR 44H FE8CH SFR 46H FE8EH SFR 47H FE90H SFR 48H FE92H SFR 49H FE94H SFR 4AH FE96H SFR 4BH F...

Страница 151: ...EBEH PECSN15 SFR 5FH PEC Segment No Register 0000H FEC0H PECC0 SFR 60H PEC Channel 0 Control Register 0000H FEC2H PECC1 SFR 61H PEC Channel 1 Control Register 0000H FEC4H PECC2 SFR 62H PEC Channel 2 C...

Страница 152: ...SFR 78H PEC Channel 0 Extended Control Register 0000H FEF2H PECXC2 SFR 79H PEC Channel 2 Extended Control Register 0000H FEF4H reserved SFR 7AH reserved do not use FEF6H reserved SFR 7BH reserved do...

Страница 153: ...N4 SFR b 8DH Bus Configuration Register 4 0000H FF1CH ZEROS SFR b 8EH Constant Value 0sRegister 0000H FF1EH ONES SFR b 8FH Constant Value 1sRegister FFFFH FF20H SFR b 90H FF22H SFR b 91H FF24H SFR b 9...

Страница 154: ...2E Timer 2 Interrupt Control Register 0000H FF62H T3IC SFR b B1H GPT12E Timer 3 Interrupt Control Register 0000H FF64H T4IC SFR b B2H GPT12E Timer 4 Interrupt Control Register 0000H FF66H T5IC SFR b B...

Страница 155: ...gister 0000H FF86H IRQ23IC SFR b C3H IRQ23 Interrupt Control Register 0000H FF88H IRQ24IC SFR b C4H IRQ24 Interrupt Control Register 0000H FF8AH IRQ25IC SFR b C5H IRQ25 Interrupt Control Register 0000...

Страница 156: ...FR b DAH FFB6H SFR b DBH FFB8H SFR b DCH FFBAH PECXISNC SFR b DDH PEC Extended Interrupt Subnode Control Register 0000H FFBCH SFR b DEH FFBEH SFR b DFH FFC0H SFR b E0H FFC2H SFR b E1H FFC4H SFR b E2H...

Страница 157: ...0000H FFF8H reserved reserved do not use 0000H FFFAH reserved reserved do not use 0000H FFFCH reserved reserved do not use 0000H FFFEH reserved reserved do not use 0000H 1 The PDBUS chip select depen...

Страница 158: ...ister 0 0000H BUSCON1 FF14H SFR b 8AH Bus Configuration Register 1 0000H BUSCON2 FF16H SFR b 8BH Bus Configuration Register 2 0000H BUSCON3 FF18H SFR b 8CH Bus Configuration Register 3 0000H BUSCON4 F...

Страница 159: ...er 10 bits 0001H DPP2 FE04H SFR 02H CPU Data Page Pointer 2 Register 10 bits 0002H DPP3 FE06H SFR 03H CPU Data Page Pointer 3 Register 10 bits 0003H DSWEVT F0F4H ESFR 7AH Specifies action if DEBUG ins...

Страница 160: ...SFR b CAH IRQ30 Interrupt Control Register 0000H IRQ31IC FF96H SFR b CBH IRQ31 Interrupt Control Register 0000H IRQ32IC FF9CH SFR b CEH IRQ32 Interrupt Control Register 0000H IRQ33IC FF9EH SFR b CFH...

Страница 161: ...176H ESFR b BBH IRQ59 Interrupt Control Register 0000H IRQ60IC F178H ESFR b BCH IRQ60 Interrupt Control Register 0000H IRQ61IC F184H ESFR b C2H IRQ61 Interrupt Control Register 0000H IRQ62IC F18CH ESF...

Страница 162: ...IC F14EH ESFR b A7H IRQ87 Interrupt Control Register 0000H IRQ88IC F150H ESFR b A8H IRQ88 Interrupt Control Register 0000H IRQ89IC F152H ESFR b A9H IRQ89 Interrupt Control Register 0000H IRQ90IC F154H...

Страница 163: ...Control Register 0000H IRQ110IC F0D4H ESFR 6AH IRQ110 Interrupt Control Register 0000H IRQ111IC F0D6H ESFR 6BH IRQ111 Interrupt Control Register 0000H MDC FF0EH SFR b 87H CPU Multiply Divide Control...

Страница 164: ...ECC9 FEEAH SFR 75H PEC Channel 9 Control Register 0000H PECC10 FEECH SFR 76H PEC Channel 10 Control Register 0000H PECC11 FEEEH SFR 77H PEC Channel 11 Control Register 0000H PECC12 FEF8H SFR 7CH PEC C...

Страница 165: ...FR 5FH PEC Segment No Register 0000H PECXC0 FEF0H SFR 78H PEC Channel 0 Extended Control Register 0000H PECXC2 FEF2H SFR 79H PEC Channel 2 Extended Control Register 0000H PECXISNC FFBAH SFR b DDH PEC...

Страница 166: ...SSC0PISEL F0B6H ESFR 5BH SSC0 Port Input Selection Register 0000H SSC0RB F0B2H ESFR 59H SSC0 Receive Buffer RO 0000H SSC0RIC FF74H SFR b BAH SSC0 Receive Interrupt Control Register 0000H SSC0TB F0B0H...

Страница 167: ...gister 0000H T6IC FF68H SFR b B4H GPT12E Timer 6 Interrupt Control Register 0000H TFR FFACH SFR b D6H Trap Flag Register 0000H WDT FEAEH SFR 57H Watchdog Timer Register RO 0000H WDTCON FFAEH SFR b D7H...

Страница 168: ...al Control Register 0000H ZEROS FF1CH SFR b 8EH Constant Value 0sRegister 0000H 1 The PDBUS chip select depends on the register type Chip select pd_cs_esfr is used for register types ESFR and ESFR b w...

Страница 169: ...interrupt nodes depends on the subsystem configuration Depending on this configured number of interrupts not all below listed interrupts are available on product level Example PARAM_IC_NODES 16 Only o...

Страница 170: ...uest 27 IRQ27IC 006CH 1BH irq_i 28 Product Interrupt Request 28 IRQ28IC 0070H 1CH irq_i 29 Product Interrupt Request 29 IRQ29IC 0074H 1DH irq_i 30 Product Interrupt Request 30 IRQ30IC 0078H 1EH irq_i...

Страница 171: ...E0H 38H irq_i 57 Product Interrupt Request 57 IRQ57IC 00E4H 39H irq_i 58 Product Interrupt Request 58 IRQ58IC 00E8H 3AH irq_i 59 Product Interrupt Request 59 IRQ59IC 00ECH 3BH irq_i 60 Product Interru...

Страница 172: ...equest 69 IRQ69IC 0154H 55H irq_i 70 Product Interrupt Request 70 IRQ70IC 0158H 56H irq_i 71 Product Interrupt Request 71 IRQ71IC 015CH 57H irq_i 72 Product Interrupt Request 72 IRQ72IC 0160H 58H irq_...

Страница 173: ...C 01CCH 73H irq_i 100 Product Interrupt Request 100 IRQ100IC 01D0H 74H irq_i 101 Product Interrupt Request 101 IRQ101IC 01D4H 75H irq_i 102 Product Interrupt Request 102 IRQ102IC 01D8H 76H irq_i 103 P...

Страница 174: ...errupt Request 21 IRQ21IC 0054H 15H irq_i 22 Product Interrupt Request 22 IRQ22IC 0058H 16H irq_i 23 Product Interrupt Request 23 IRQ23IC 005CH 17H irq_i 24 Product Interrupt Request 24 IRQ24IC 0060H...

Страница 175: ...errupt Request 53 IRQ53IC 00D4H 35H irq_i 54 Product Interrupt Request 54 IRQ54IC 00D8H 36H irq_i 55 Product Interrupt Request 55 IRQ55IC 00DCH 37H irq_i 56 Product Interrupt Request 56 IRQ56IC 00E0H...

Страница 176: ...errupt Request 82 IRQ82IC 0188H 62H irq_i 83 Product Interrupt Request 83 IRQ83IC 018CH 63H irq_i 84 Product Interrupt Request 84 IRQ84IC 0190H 64H irq_i 85 Product Interrupt Request 85 IRQ85IC 0194H...

Страница 177: ...H irq_i 104 Product Interrupt Request 104 IRQ104IC 01E0H 78H irq_i 105 Product Interrupt Request 105 IRQ105IC 01E4H 79H irq_i 106 Product Interrupt Request 106 IRQ106IC 01E8H 7AH irq_i 107 Product Int...

Страница 178: ...User s Manual C166S V1 SubSystem Memory Organization User s Manual 4 52 V 1 6 2001 08...

Страница 179: ...timize instruction sequences in terms of code size and or execution time Note Both ordering schemes hexadecimal opcode and mnemonic are provided in more detailed lists in the following sections of thi...

Страница 180: ...CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS PCALL MOV x3 MOVB x4 MOV MOV MOVB MOVB MOV MOV MOVB MOVB x5 DIS WDT EINIT MOVBZ MOVBS x6 CMPI1 CMPI2 CMPD1 CMPD2 SCXT SCXT MOV MOV x7 IDLE PWRDN SRV WDT SRST EXTP S...

Страница 181: ...except for the arithmetic logical and compare instructions where only R0 to R3 are allowed bitaddr Direct bit in the bit addressable memory area bitoff Direct word in the bit addressable memory area...

Страница 182: ...nch Condition Codes cc Symbolically specifiable condition codes cc_UC Unconditional cc_Z Zero cc_NZ Not Zero cc_V Overflow cc_NV No Overflow cc_N Negative cc_NN Not Negative cc_C Carry cc_NC No Carry...

Страница 183: ...VN BOR BXOR bitaddrZ z bitaddrQ q 4 CMP B Rwn Rwm 1 Rwn Rwi 1 Rwn Rwi 1 Rwn data3 1 reg data16 2 reg mem 2 2 2 2 4 4 BCLR BSET bitaddrQ q 2 CALLA JMPA cc caddr 4 BFLDH BFLDL bitoffQ mask8 data8 4 CALL...

Страница 184: ...ct register 4 ADDB reg mem Add direct byte memory to direct register 4 ADDB mem reg Add direct byte register to direct memory 4 ADDC Rw Rw Add direct word GPR to direct GPR with Carry 2 ADDC Rw Rw Add...

Страница 185: ...a from direct register 4 SUBB reg mem Subtract direct byte memory from direct register 4 SUBB mem reg Subtract direct byte register from direct memory 4 SUBC Rw Rw Subtract direct word GPR from direct...

Страница 186: ...itwise AND direct word GPR with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR and post increment source pointer b...

Страница 187: ...e OR direct byte memory with direct register 4 ORB mem reg Bitwise OR direct byte register with direct memory 4 XOR Rw Rw Bitwise XOR direct word GPR with direct GPR 2 XOR Rw Rw Bitwise XOR indirect w...

Страница 188: ...ct GPR 2 CMP Rw Rw Compare indirect word memory to direct GPR 2 CMP Rw Rw Compare indirect word memory to direct GPR and post increment source pointer by 2 2 CMP Rw data3 Compare immediate word data t...

Страница 189: ...4 CMPI1 Rw mem Compare direct word memory to direct GPR and increment GPR by 1 4 CMPI2 Rw data4 Compare immediate word data to direct GPR and increment GPR by 2 2 CMPI2 Rw data16 Compare immediate wor...

Страница 190: ...specified by immediate data 2 Data Movement MOV Rw Rw Move direct word GPR to direct GPR 2 MOV Rw data4 Move immediate word data to direct GPR 2 MOV reg data16 Move immediate word data to direct regis...

Страница 191: ...indirect memory 2 MOVB Rw Rw Move indirect byte memory to indirect memory 2 MOVB Rw Rw Move indirect byte memory to indirect memory and post increment destination pointer by 1 2 MOVB Rw Rw Move indire...

Страница 192: ...ddr rel Jump relative if direct bit is not set 4 JNBS bitaddr rel Jump relative and set bit if direct bit is not set 4 CALLA cc caddr Call absolute subroutine if condition is met 4 CALLI cc Rw Call in...

Страница 193: ...Watchdog Timer 4 EINIT Signify End of Initialization on RSTOUT pin 4 ATOMIC irang2 Begin ATOMIC sequence 2 EXTR irang2 Begin EXTended Register sequence 2 EXTP Rw irang2 Begin EXTended Page sequence 2...

Страница 194: ...o R3 can be used as indirect address pointers 2 These instructions are encoded by means of additional bits in the operand field of the instruction 00xx xxxxB EXTS or ATOMIC 01xx xxxxB EXTP 10xx xxxxB...

Страница 195: ...w 2B 2 PRIOR Rw Rw 0C 2 ROL Rw Rw 2C 2 ROR Rw Rw 0D 2 JMPR cc_UC rel 2D 2 JMPR cc_EQ rel or cc_Z rel 0E 2 BCLR bitoff 0 2E 2 BCLR bitoff 2 0F 2 BSET bitoff 0 2F 2 BSET bitoff 2 10 2 ADDC Rw Rw 30 2 SU...

Страница 196: ...4B 2 DIV Rw 6B 2 DIVL Rw 4C 2 SHL Rw Rw 6C 2 SHR Rw Rw 4D 2 JMPR cc_V rel 6D 2 JMPR cc_N rel 4E 2 BCLR bitoff 4 6E 2 BCLR bitoff 6 4F 2 BSET bitoff 4 6F 2 BSET bitoff 6 50 2 XOR Rw Rw 70 2 OR Rw Rw 5...

Страница 197: ...addr rel 8B AB 2 CALLI cc Rw 8C AC 2 ASHR Rw Rw 8D 2 JMPR cc_C rel or cc_ULT rel AD 2 JMPR cc_SGT rel 8E 2 BCLR bitoff 8 AE 2 BCLR bitoff 10 8F 2 BSET bitoff 8 AF 2 BSET bitoff 10 90 2 CMPI2 Rw data4...

Страница 198: ...2 RETP reg CC 2 NOP EC 2 PUSH reg CD 2 JMPR cc_SLT rel ED 2 JMPR cc_UGT rel CE 2 BCLR bitoff 12 EE 2 BCLR bitoff 14 CF 2 BSET bitoff 12 EF 2 BSET bitoff 14 D0 2 MOVBS Rw Rb F0 2 MOV Rw Rw D1 2 ATOMIC...

Страница 199: ...All of the available addressing modes are summarized at the end of each single instruction description In contrast to the syntax for the instructions described in the following the assembler provides...

Страница 200: ...Pointer MD Multiply Divide register 32 bits wide consists of MDH and MDL MDL MDH Multiply Divide Low and High registers each 16 bit wide PSW Program Status Word SP System Stack Pointer SYSCON SYSCON C...

Страница 201: ...cified condition exists and is skipped if it does not The table below summarizes the 16 possible condition codes that can be used within Call and Branch instructions The table shows the abbreviations...

Страница 202: ...1 Result equals zero Z 0 Result does not equal zero E 1 Source operand represents the lowest negative number either 8000h for word data or 80h for byte data E 0 Source operand does not represent the...

Страница 203: ...ndition flags of this instruction as usual Addressing Modes This part specifies which combinations of different addressing modes are available for the required operands The selected addressing mode co...

Страница 204: ...p number trap7 QQ 8 bit word address of the source bit bitoff rr 8 bit relative target address word offset rel RR 8 bit word address reg ZZ 8 bit word address of the destination bit bitoff 8 bit immed...

Страница 205: ...on The following pages of this section contain a detailed description of each instruction in alphabetical order Bits in ascending order LSB MSB Representation in the Assembler Listing N2N1 N4N3 N6N5 N...

Страница 206: ...User s Manual C166S V1 SubSystem Instruction Set User s Manual 5 28 V 1 6 2001 08...

Страница 207: ...C166S V1 SubSystem Detailed Instruction Set User s Manual 6 1 V 1 6 2001 08 6 Detailed Instruction Set The following pages of this section contain a detailed description of each instruction in alphab...

Страница 208: ...f op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the...

Страница 209: ...p2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the res...

Страница 210: ...rithmetic CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set...

Страница 211: ...hmetic CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cl...

Страница 212: ...specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result...

Страница 213: ...cified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result eq...

Страница 214: ...of the result are filled with zeros if the original most significant bit was a 0 or with ones if the original most significant bit was a 1 The Overflow flag is used as a Rounding flag The least signi...

Страница 215: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 9 V 1 6 2001 08 Encoding Mnemonic Format Bytes ASHR Rwn data4 BC n 2 ASHR Rwn Rwm AC nm 2...

Страница 216: ...s and class A hardware traps to be disabled for a specified number of instructions The ATOMIC instruction becomes immediately active No NOPs are required for normal ATOMIC execution Depending on the v...

Страница 217: ...forms a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Always cleared Z Contains the logical NOR of the...

Страница 218: ...erand s op1 BIT Operation op1 0 Description Clears the bit specified by op1 This instruction is primarily used for peripheral and system control CPU Flags E Always cleared Z Contains the logical negat...

Страница 219: ...it comparison of the source bit specified by op1 and the source bit specified by op2 No result is written by this instruction Only the flags are updated CPU Flags E Always cleared Z Contains the logic...

Страница 220: ...1 op1 count 8 op3 count ENDIF count count 1 END WHILE Description Replaces those bits in the high byte of the destination word operand op1 which are selected by an 1 in the mask specified by op2 with...

Страница 221: ...t 1 op1 count op3 count ENDIF count count 1 END WHILE Description Replaces those bits in the low byte of the destination word operand op1 which are selected by an 1 in the mask specified by op2 with t...

Страница 222: ...ration op1 op2 Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly CP...

Страница 223: ...ion op1 op2 Description Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated...

Страница 224: ...orms a single bit logical OR of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Always cleared Z Contains the logical NOR of the t...

Страница 225: ...ource Operand s none Destination Operand s op1 BIT Operation op1 1 Description Sets the bit specified by op1 CPU Flags E Always cleared Z Contains the logical negation of the previous state of the spe...

Страница 226: ...s a single bit logical EXCLUSIVE OR of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Always cleared Z Contains the logical NOR o...

Страница 227: ...is met a branch to the absolute memory location specified by the second operand op2 is taken The value of the instruction pointer IP is placed into the system stack Because the IP always points to th...

Страница 228: ...op1 is met a branch to the location specified indirectly by the second operand op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the...

Страница 229: ...isplacement is a two s complement number which is sign extended and counts the relative distance in words The value of the instruction pointer IP is placed into the system stack Because the IP always...

Страница 230: ...tion specified by op2 within the segment specified by op1 The previous value of the CSP is placed into the system stack to insure correct return to the calling segment The value of the instruction poi...

Страница 231: ...ules of subtraction The operands remain unchanged CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result...

Страница 232: ...s of subtraction The operands remain unchanged CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result eq...

Страница 233: ...ters Once the subtraction has completed the operand op1 is decremented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level l...

Страница 234: ...ters Once the subtraction has completed the operand op1 is decremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level l...

Страница 235: ...ters Once the subtraction has completed the operand op1 is incremented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level l...

Страница 236: ...ters Once the subtraction has completed the operand op1 is incremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level l...

Страница 237: ...ion Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 CPU Flags E Set if the value of op1 represents the lowest possible negative number Cleared other...

Страница 238: ...tion Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 CPU Flags E Set if the value of op1 represents the lowest possible negative number Cleared othe...

Страница 239: ...tion can be executed at any time between the Reset and the first execution of either EINIT or SRVWDT Once either an EINIT or a SRVWDT has been executed the DISWDT instruction will have no effect If th...

Страница 240: ...nt is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Always cleared Z Set if quotient stored in the MDL...

Страница 241: ...uotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Always cleared Z Set if quotient stored in the...

Страница 242: ...ed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Always cleared Z Set if quotient stored in...

Страница 243: ...MD register by the source word operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH C...

Страница 244: ...INIT instruction has been executed at which time it goes high This enables the software to signal the external circuitry that it has successfully initialized the microcontroller Execution of the Disab...

Страница 245: ...dressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTP...

Страница 246: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 40 V 1 6 2001 08 Encoding Mnemonic Format Bytes EXTP pag irang2 D7 01 0 pp 0 00pp 4 EXTP Rwm irang2 DC 01 m 2...

Страница 247: ...rides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR...

Страница 248: ...anual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 42 V 1 6 2001 08 C Not affected N Not affected Encoding Mnemonic Format Bytes EXTPR pag irang2 D7 11 0 pp 0 00pp 4 EXTPR Rwm irang2 DC...

Страница 249: ...TRUE Next Instruction count count 1 END WHILE count 0 SFR_range Standard Enable interrupts and traps Description Causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being...

Страница 250: ...andard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are loc...

Страница 251: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 45 V 1 6 2001 08 Encoding Mnemonic Format Bytes EXTS seg irang2 D7 00 0 ss 00 4 EXTS Rwm irang2 DC 00 m 2...

Страница 252: ...dressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified num...

Страница 253: ...C166S V1 SubSystem Detailed Instruction Set User s Manual 6 47 V 1 6 2001 08 V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes EXTSR seg irang2 D7 10 0 ss 00 4 EXTSR Rwm ira...

Страница 254: ...nstruction causes the part to enter the idle mode In this mode the CPU is powered down while the peripherals remain running It remains powered down until a peripheral interrupt or external interrupt o...

Страница 255: ...es at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The...

Страница 256: ...op2 The bit specified by op1 is cleared allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words...

Страница 257: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 51 V 1 6 2001 08 Encoding Mnemonic Format Bytes JBC bitaddrQ q rel AA QQ rr q0 4...

Страница 258: ...and s none Operation IF op1 1 THEN IP op2 ELSE Next Instruction END IF Description If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition...

Страница 259: ...Operation IF op1 1 THEN IP op2 ELSE Next Instruction END IF Description If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met...

Страница 260: ...execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative dist...

Страница 261: ...e Operand s op1 segment number op2 16 bit address offset Destination Operand s none Operation CSP op1 IP op2 Description Branches unconditionally to the absolute address specified by op2 within the se...

Страница 262: ...tinues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words...

Страница 263: ...1 is set allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the...

Страница 264: ...moved data is examined and the flags are updated accordingly CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z S...

Страница 265: ...tion Set User s Manual 6 59 V 1 6 2001 08 MOV Rwm Rwn B8 nm 2 MOV Rwn Rwm D8 nm 2 MOV Rwn Rwm E8 nm 2 MOV Rwn Rwm C8 nm 2 MOV Rwn mem 84 0n MM MM 4 MOV mem Rwn 94 0n MM MM 4 MOV mem reg F6 RR MM MM 4...

Страница 266: ...oved data is examined and the flags are updated accordingly CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set...

Страница 267: ...Set User s Manual 6 61 V 1 6 2001 08 MOVB Rwm Rbn B9 nm 2 MOVB Rwn Rwm D9 nm 2 MOVB Rwn Rwm E9 nm 2 MOVB Rwn Rwm C9 nm 2 MOVB Rwn mem A4 0n MM MM 4 MOVB mem Rwn B4 0n MM MM 4 MOVB mem reg F7 RR MM MM...

Страница 268: ...n extends the contents of the source byte operand specified by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated ac...

Страница 269: ...es and zero extends the contents of the source byte operand specified by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the flags are...

Страница 270: ...16 bit by 16 bit signed multiplication using the two words specified by operands op1 and op2 respectively The signed 32 bit result is placed in the MD register CPU Flags E Always cleared Z Set if resu...

Страница 271: ...16 bit by 16 bit unsigned multiplication using the two words specified by operands op1 and op2 respectively The unsigned 32 bit result is placed in the MD register CPU Flags E Always cleared Z Set if...

Страница 272: ...d by op1 The result is then stored in op1 CPU Flags E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals...

Страница 273: ...ed by op1 The result is then stored in op1 CPU Flags E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals...

Страница 274: ...P Source Operand s none Destination Operand s none Operation No Operation Description This instruction causes a null operation to be performed A null operation causes no change in the status of the fl...

Страница 275: ...d specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if resu...

Страница 276: ...pecified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result...

Страница 277: ...o the system stack and branches to the absolute memory location specified by the second operand op2 Because IP always points to the instruction following the branch instruction the value stored on the...

Страница 278: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 72 V 1 6 2001 08 Encoding Mnemonic Format Bytes PCALL reg caddr E2 RR MM MM 4...

Страница 279: ...em stack specified by the Stack Pointer into the operand specified by op1 The Stack Pointer is then incremented by two CPU Flags E Set if the value of the popped word represents the lowest possible ne...

Страница 280: ...n stores a count value in the word operand specified by op1 This count value indicates the number of single bit shifts required to normalize the word operand op2 so that its most significant bit is eq...

Страница 281: ...he location in the system stack specified by the Stack Pointer after the Stack Pointer has been decremented by two CPU Flags E Set if the value of the pushed operand op1 represents the lowest possible...

Страница 282: ...this mode all peripherals and the CPU are powered down until the part is externally reset To insure that this instruction is not accidentally executed it is implemented as a protected instruction To f...

Страница 283: ...roup Return Instructions Syntax RET Source Operand s none Destination Operand s none Operation IP SP SP SP 2 Description Returns from a subroutine The IP is popped from the system stack CPU Flags E No...

Страница 284: ...W SP SP SP 2 Description Returns from an interrupt routine The IP CSP and PSW are popped off the system stack The CSP is only popped if segmentation is enabled This is indicated by the SGTDIS bit in t...

Страница 285: ...First the IP is popped from the system stack and then the next word is popped from the system stack into the operand specified by op1 CPU Flags E Set if the value of the popped word represents the lo...

Страница 286: ...nstructions Syntax RETS Source Operand s none Destination Operand s none Operation IP SP SP SP 2 CSP SP SP SP 2 Description Returns from an inter segment subroutine The IP and CSP are popped from the...

Страница 287: ...he destination word operand op1 the number of times as specified by the source operand op2 Bit 15 is rotated into Bit 0 and into the Carry Only shift values between 0 and 15 are allowed When using a G...

Страница 288: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 82 V 1 6 2001 08 Encoding Mnemonic Format Bytes ROL Rwn data4 1C n 2 ROL Rwn Rwm 0C nm 2...

Страница 289: ...r of times as specified by the source operand op2 Bit 0 is rotated into Bit 15 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least si...

Страница 290: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 84 V 1 6 2001 08 Encoding Mnemonic Format Bytes ROR Rwn data4 3C n 2 ROR Rwn Rwm 2C nm 2...

Страница 291: ...P 2 SP tmp1 op1 tmp2 Description Switches contexts of any register Switching context is a push and load operation The contents of the register specified by the first operand op1 are pushed onto the st...

Страница 292: ...times as specified by the source operand op2 The least significant bits of the result are filled with zeros accordingly The least The most significant bit is shifted into the Carry Only shift values...

Страница 293: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 87 V 1 6 2001 08 Encoding Mnemonic Format Bytes SHL Rwn data4 5C n 2 SHL Rwn Rwm 4C nm 2...

Страница 294: ...ordingly Since the bits shifted out effectively represent the remainder the Overflow flag is used instead as a Rounding flag A shift right is a division by a power of two The overflow flag with the ca...

Страница 295: ...1 6 2001 08 C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared oth...

Страница 296: ...Description This instruction is used to perform a software reset A software reset has the same effect on the microcontroller as an externally applied hardware reset To insure that this instruction is...

Страница 297: ...r Description This instruction reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte Once this instruction has been executed the watchdog timer cannot be disabl...

Страница 298: ...Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic...

Страница 299: ...ags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic un...

Страница 300: ...to perform multiple precision arithmetic CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals...

Страница 301: ...erform multiple precision arithmetic CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero...

Страница 302: ...1 The invoked routine is determined by branching to the specified vector table entry point This routine has no indication of whether it was called by software or hardware System state is preserved ide...

Страница 303: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 97 V 1 6 2001 08 Encoding Mnemonic Format Bytes TRAP trap7 9B t ttt0 2...

Страница 304: ...n operand specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set...

Страница 305: ...perand specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if...

Страница 306: ...User s Manual C166S V1 SubSystem Detailed Instruction Set User s Manual 6 100 V 1 6 2001 08...

Страница 307: ...clocked into the input latch once per state time regardless whether the port is configured for input or output Figure 7 1 SFRs associated with the Parallel Ports A write operation to a port pin confi...

Страница 308: ...n by writing to the port output register On most of the port lines the user software is responsible for setting the proper direction when using an alternate input or output function of a pin This is d...

Страница 309: ...4 05H 05H Initial output level is high BFLDL DP4 05H 05H Switch on the output drivers Note When using several BSET pairs to control more pins of one port these pairs must be separated by instructions...

Страница 310: ...nd for the high byte of the word During write cycles PORT0 outputs the data byte or word after outputting the address P0H PORT0 High Register SFR FF02H 81H Reset value 00H 15 14 13 12 11 10 9 8 7 6 5...

Страница 311: ...segment address or the 8 16 bit data information The incoming data on PORT0 is read on the line Alternate Data Input While an external bus mode is enabled the user software should not write to the por...

Страница 312: ...08 The figure below shows the structure of a PORT0 pin Figure 7 3 Block Diagram of a PORT0 Pin P0H 7 0 P0L 7 0 Port Output Register 0 1 0 1 Driver Clock Pin Direction Register 0 1 Input Register Inte...

Страница 313: ...8 7 6 5 4 3 2 1 0 P1L 7 P1L 6 P1L 5 P1L 4 P1L 3 P1L 2 P1L 1 P1L 0 rw rw rw rw rw rw rw rw P1H PORT1 High Register SFR FF06H 83H Reset Value 00H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P1H 7 P1H 6 P1H 5...

Страница 314: ...ata into the port output register are controlled by the bus controller hardware The input of the port output register is disconnected from the internal bus and is switched to the line labeled Alternat...

Страница 315: ...s The upper 4 pins of PORT1 combine internal bus data and alternate data output before the port register input Figure 7 5 Block Diagram of a PORT1 Pin with Address Function Port Output Register 0 1 0...

Страница 316: ...address lines are selected the alternate function of Port 4 may be necessary to access e g external memory directly after reset For this reason Port 4 will be switched to this alternate function autom...

Страница 317: ...LSEL 10 16 MB P4 0 P4 1 P4 2 P4 3 P4 4 P4 5 P4 6 P4 7 Gen purpose IO Gen purpose IO Gen purpose IO Gen purpose IO Gen purpose IO Gen purpose IO Gen purpose IO Gen purpose IO Seg Address A16 Seg Addres...

Страница 318: ...User s Manual 7 12 V 1 6 2001 08 Figure 7 7 Block Diagram of a Port 4 Pin P4 7 0 Port Output Register 0 1 0 1 Driver Clock Pin Direction Register 0 1 Input Register Internal Bus AltDataIn AltDataOut A...

Страница 319: ...6 The number of chip select signals is selected via conf_rst_cssel_i 1 0 CSSEL during reset P6 3RUW DWD 5HJLVWHU SFR FFCCH E6H Reset Value 00H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P6 7 P6 6 P6 5 P6...

Страница 320: ...s before Thus the alternate function CS is selected automatically in this case Table 7 3 Alternate Functions of Port 6 Port 6 Pin Altern Function CSSEL 10 Altern Function CSSEL 01 Altern Function CSSE...

Страница 321: ...15 V 1 6 2001 08 Figure 7 9 Block Diagram of Port 6 Pins with an alternate output function P6 4 0 Port Output Register 0 1 0 1 Driver Clock Pin Direction Register 0 1 Input Register Internal Bus AltDa...

Страница 322: ...rts User s Manual 7 16 V 1 6 2001 08 Figure 7 10 Block Diagram of Port 6 Pins without an alternate output function P6 7 5 Port Output Register Driver Clock Pin Direction Register 0 1 Input Register In...

Страница 323: ...th 16 bit 8 bit chip selects and length waitstates READY control ALE RW delay These parameters are used for accesses within a specific address area that is defined via the corresponding register ADDRS...

Страница 324: ...d bit BUSACTx 1 and configured bitfield BTYP the C166S uses a subset of its port lines together with some control lines to build the external bus The bus configuration BTYP for the address windows BUS...

Страница 325: ...n Port 4 if segmentation is enabled and do not require latches The EBC initiates an external access by generating the Address Latch Enable ALE signal and then placing an address on the bus The falling...

Страница 326: ...rmal ALE Normal ALE Cycle 5 CSxL6 Data Out Extend ALE WRL WRH WR WRCS Extended ALE Cycle 5 D15 D0 Norm ALE 1 3 MCTC Low Address Data Out D15 D0 Extd ALE Low Address 2 1 Section 8 3 4 Read Write Delay...

Страница 327: ...E6 CLKOUT Normal ALE Normal ALE Cycle 5 CSxL6 Extend ALE RD RDCS Extended ALE Cycle 5 1 3 MCTC 4 MTTC Data In Low Address D15 D0 Norm ALE D15 D0 Extd ALE Data In Low Address 1 Section 8 3 4 Read Write...

Страница 328: ...iod of time the EBC activates the appropriate command signal RD WR WRL WRH Data is driven onto the data bus either by the EBC for write cycles or by the external memory peripheral for read cycles Afte...

Страница 329: ...xE6 D15 D0 Normal Wr CLKOUT Normal ALE Normal ALE Cycle 5 CSxL6 Data Out Extend ALE WRL WRH WR WRCS Extended ALE Cycle 5 D15 D0 Early Write 1 3 MCTC 2 1 Section 8 3 4 Read Write Delay 2 Section 8 3 5...

Страница 330: ...ad Access Valid A23 A0 BHE CSxE6 CLKOUT Normal ALE Normal ALE Cycle 5 CSxL6 Extend ALE RD RDCS Extended ALE Cycle 5 1 3 MCTC 4 MTTC Data In D15 D0 1 Section 8 3 4 Read Write Delay 3 Section 8 3 2 Memo...

Страница 331: ...ses a multiplexed bus mode This allows an external address decoder to be connected to PORT1 only while using it for all kinds of bus cycles Note Never change the configuration for an address area that...

Страница 332: ...clock frequency In such a case an additional waitstate can automatically be inserted when leaving a certain address window i e when the next cycle accesses a different window This waitstate is contro...

Страница 333: ...hat has a single CS input and two WR enable inputs for the two bytes the EBC can generate these two write control signals directly This saves the external combination of the WR signal with A0 or BHE I...

Страница 334: ...ignal is not used Segment Address Generation During external accesses the EBC generates a programmable number of address lines on Port 4 which extend the 16 bit address output on PORT0 and thus increa...

Страница 335: ...ponding valid CS signal is determined and activated All other CS lines are deactivated driven high at the same time Note The CSx signals will not be updated for an access to any internal address area...

Страница 336: ...rotocol diagrams CSCFG 0 becomes active with the falling edge of ALE and becomes inactive at the beginning of an external bus cycle that accesses a different address window No spikes will be generated...

Страница 337: ...llows implementation of a large sequential memory area and access to a great number of external devices using an external decoder By increasing the number of CS lines the C166S can access memory banks...

Страница 338: ...after its falling edge Memory Cycle Time extendable with 1 15 waitstates defines the allowable access time Memory Tri State Time extendable with 1 waitstate defines the time for a data driver to float...

Страница 339: ...his access is required for the execution of the current instruction The memory cycle time waitstates can be programmed in increments of one CPU clock 2 TCL within a range from 0 to 15 default after re...

Страница 340: ...w in the standard way but can be deactivated driven high one TCL earlier than defined in the standard timing In this case the data output drivers will also be deactivated one TCL earlier This is espec...

Страница 341: ...multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time The READY function is enabled via the ReaDY ENable RDYENx bits in the BUSCON registers When this fu...

Страница 342: ...l already be low for a peripheral access it may be delayed As memories tend to be faster than peripherals there should be no impact on system performance When using the READY function with so called n...

Страница 343: ...ccesses that are not covered by these four areas are then controlled via BUSCON0 This allows the use of memory components or peripherals with different interfaces within the same system while optimizi...

Страница 344: ...Clock Enable CLKOUT cleard after reset 0 CLKOUT disabled pin may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS 9 rwh Disable Enable Control for Pin BHE Set...

Страница 345: ...ter reset is partly controlled by hardware i e it is initialized via dedicated configuration signals during the reset sequence This hardware control allows an appropriate external bus to be defined fo...

Страница 346: ...0 CSW EN1 CSR EN1 0 RDY EN1 BSW C1 BUS ACT 1 ALE CTL 1 EW EN1 BTYP MTT C1 RWD C1 MCTC rw rw r rw rw rw rw rw rw rw rw rw BUSCON2 Bus Control Register 2 SFR FF16H 8BH Reset value 0000H 15 14 13 12 11 1...

Страница 347: ...delay activate command with falling edge of ALE MTTCx 5 rw Memory Tristate Time Control 0 1 waitstate 1 No waitstate BTYP 7 6 rw External Bus Configuration 00 8 bit Demultiplexed Bus 01 8 bit Multiple...

Страница 348: ...enerated for the duration of the read command CSWENx 15 rw Write Chip Select Enable 0 The CS signal is independent of the write cmd WR WRL WRH 1 The CS signal is generated for the duration of the writ...

Страница 349: ...H 0EH Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw ADDRSEL4 Address Select Register 4 SFR FE1EH 0FH Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw...

Страница 350: ...s small areas may be cut out of bigger windows for example in order to utilize external resources effectively especially within segment 0 For each access the EBC compares the current address with all...

Страница 351: ...ternal area using the corresponding BUSCONx register Priority of the ADDRSELx registers ADDRSEL2 priority II 1 ADDRSEL4 II 2 ADDRSEL1 II 3 ADDRSEL3 II 4 Priority 3 If there is no match with any XADRSx...

Страница 352: ...Rs or SFRs etc are used the external bus interface does not change seeTable 8 7 below Accesses to on chip X Peripherals are also controlled by the EBC However even though an X Peripheral appears to th...

Страница 353: ...C166S acknowledges this request via the HLDA output and will float its bus lines in this case The CS outputs provide internal pull up devices The new master may now access the peripheral devices or m...

Страница 354: ...only the next HOLD request is not answered Connecting two C166Ss in this way would require additional logic to combine the respective output signals HLDA and BREQ This can be avoided by switching one...

Страница 355: ...ow Figure 8 11 Sharing External Resources Using Slave Mode When the bus arbitration is enabled HLDEN 1 the three corresponding pins are controlled automatically by the EBC Normally the respective port...

Страница 356: ...red to this figure The Figure 8 12 shows the first possibility for BREQ to go active During bus hold pin P3 12 is switched back to its standard function and is then controlled by DP3 12 and P3 12 DP3...

Страница 357: ...ain sequence is initiated by HOLD going high BREQ and HOLD are connected via an external arbitration circuitry HOLD may also be deactivated without the C166S requesting the bus 8 7 The XBUS Interface...

Страница 358: ...ERCON register define which on chip peripherals are enabled or disabled xpercon_o 15 0 If a peripheral is disabled all it s addresses are no more visible The XPERCON register is accessible until execu...

Страница 359: ...al address range if XADRS1 to XADRS4 is used The upper four address lines A23 A20 are set to zero Note that the range start address can be located only on boundaries specified by the selected range si...

Страница 360: ...1 11xx 256 Byte 512 Bytes 1 KBytes 2 KBytes 4 KBytes 8 KBytes 16 KBytes 32 KBytes 64 KBytes 128 KBytes 256 KBytes 512 KBytes reserved RRRR RRRR RRRR RRRR RRRR RRR0 RRRR RRRR RR00 RRRR RRRR R000 RRRR R...

Страница 361: ...e Disable also is controlled with XPERCON and SYSCON registers BSWCx 11 rw BUSCON Switch Control 0 Address windows are switched immediately 1 A tristate waitstate is inserted if the next bus cycle acc...

Страница 362: ...User s Manual C166S V1 SubSystem The External Bus Interface User s Manual 8 40 V 1 6 2001 08...

Страница 363: ...timer can be used as a running timer and generates a periodical interrupt request with the occurrence of a timer overflow In case of an overflow the WDT counter is automatically reloaded Nevertheless...

Страница 364: ...t as well But nevertheless the whole subsystem including the WDT itself will be reseted WDT Interrupt mode If the TIMEN bit is set only the generation of watchdog timer resets is surpressed after the...

Страница 365: ...imer is programmable in two ways the input frequency to the watchdog timer can be selected via a prescaler controlled by bits WDTPRE and WDTIN in register WDTCON to be fPD 2 fPD 4 fPD 128 or fPD 256 t...

Страница 366: ...et In case of a hardware reset the software and watchdog timer reset are surpressed and not visible Software Reset is indicated after a reset was triggered by the execution of instruction SRST Watchdo...

Страница 367: ...hangeable to work with parallel busses of different width and with different protocols Features Full duplex asynchronous operating modes 8 or 9 bit data frames LSB first Parity bit generation checking...

Страница 368: ...nel Registers All ASC registers are located in the SFR ESFR memory space The respective SFR addresses can be found in list of SFRs ASC Module Interrupt Control Port Control Clock Control Address Decod...

Страница 369: ...the receiver input selection of the ASC module PISEL Port Input Select Register Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RIS r rw Field Bits Typ Description RIS 0 rw Receiver Input S...

Страница 370: ...ram of the ASC with its operating modes asynchronous and synchronous mode Figure 10 3 Block Diagram of the ASC fclk Baudrate Timer Serial Port Control Receive Transmit buffers and Shift Registers RXD...

Страница 371: ...ck to back without gaps Data reception is enabled by the Receiver Enable Bit CON_REN After reception of a character has been completed the received data can be read from the read only Receive Buffer r...

Страница 372: ...n M 2 0 rw Mode Control 000 8 bit data for synchronous operation 001 8 bit data for asynchronous operation 010 Reserved Do not use this combination 011 7 bit data and parity for asynchronous operation...

Страница 373: ...r OEN 1 Must be cleared by software FDE 11 rw Fractional Divider Enable 0 Fractional divider disabled 1 Fractional divider enabled and used as perscaler for baudrate generator bit BRS is don t care OD...

Страница 374: ...2001 08 LB 14 rw Loopback Mode Enabled 0 Loopback Mode disabled Standard transmit receive Mode 1 Loopback Mode enabled R 15 rw Baudrate Generator Run Control Bit 0 Baudrate generator disabled ASC inac...

Страница 375: ...re 10 4 shows the block diagram of the ASC when operating in Asynchronous Mode Figure 10 4 Asynchronous Mode of Serial Channel ASC 16 2 fclk R 13 Bit Reload Register 13 Bit Baudrate Timer 3 Fractional...

Страница 376: ...RBUF 7 Figure 10 5 Asynchronous 8 Bit Frames 9 Bit Data Frames 9 bit data frames consist of either nine data bits D8 D0 CON_M 100B eight data bits D7 D0 plus an automatically generated parity bit CON...

Страница 377: ...bit CON_M 0 to enable it to also receive the data bytes that will be coming having the wake up bit cleared The slaves not being addressed remain in 8 bit data wake up bit mode ignoring the following...

Страница 378: ...circuit is reset and waits for the next 1 to 0 transition at line RXD If the start bit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift re...

Страница 379: ...o the receive FIFO register only if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred RBUF Receive Buffer Register Reset...

Страница 380: ...M 000B Eight data bits are transmitted or received synchronous to a shift clock generated by the internal baudrate generator The shift clock is active only as long as data bits are transmitted or rece...

Страница 381: ...to the receive shift register synchronous to the clock that is output at TXD After the eighth bit has been shifted in the contents of the receive shift register are transferred to the receive data buf...

Страница 382: ...ed Figure 10 8 ASC Synchronous Mode Waveforms Shift Latch Shift Latch Valid Shift Valid Data n 2 Shift Clock TXD Transmit Data RXD Shift Clock TXD Transmit Data RXD Receive Data RXD Valid Data n Recei...

Страница 383: ...ter BG is the dual function Baudrate Generator Reload register Reading BG returns the contents of the timer BR_VALUE bits 15 13 return zero while writing to BG always updates the reload register bits...

Страница 384: ...nal divider asynchronous mode only It is also used for reference clock generation of the autobaud detection unit Field Bits Typ Description BR_VALUE 12 0 rw Baudrate Timer Reload Value Reading returns...

Страница 385: ...der ratios CON_FDE 0 and the required reload value for a given baudrate can be determined by the following formulas Table 10 1 Asynchronous Baudrate Formulas using the Fixed Input Clock Dividers FDE B...

Страница 386: ...he module clock fclk by a programmable divider If CON_FDE is set the fractional divider is activated It divides fclk by a fraction of n 512 for any value of n from 0 to 511 If n 0 the divider ratio is...

Страница 387: ...ure 10 10 Table 10 3 Asynchronous Baudrate Formulas using the Fractional Input Clock Divider FDE BRS BG FDV Formula 1 1 8191 1 511 0 Table 10 4 Typical Asynchronous Baudrates using the Fractional Inpu...

Страница 388: ...5 BG represents the contents of the reload register BR_VALUE taken as an unsigned 13 bit integers The maximum baudrate that can be achieved in synchronous mode when using a module clock of 60 MHz is 7...

Страница 389: ...N_OE is set indicating that the error interrupt request is due to an overrun error Asynchronous and Synchronous Mode 10 3 5 Interrupts Four interrupt sources are provided for serial channel ASC Line T...

Страница 390: ...mit data provides the time to transmit a complete frame for the service routine as TBUF may be reloaded while the previous data is still being transmitted Figure 10 11 ASC Interrupt Generation As show...

Страница 391: ...unication with SPI compatible devices Transmission and reception of data is double buffered A 16 bit baudrate generator provides the SSC with a separate serial clock signal Features Master and Slave M...

Страница 392: ...el Figure 11 2 SSC Kernel Registers All SSC registers are located in the SFR ESFR memory space The respective SFR addresses can be found in list of SFRs SSC Module Interrupt Control Port Control Clock...

Страница 393: ...The high speed synchronous serial interface can be configured in a very flexible way so it can be used with other synchronous serial interfaces can serve for master slave or multimaster interconnecti...

Страница 394: ...el SSC Block Diagram fclk Internal Bus Baudrate Generator Clock Control SSC Control Block Register CON SS_CLK RIR TIR EIR Receive Int Request Transmit Int Request Error Int Request Control Status TXD...

Страница 395: ...tions or status flags and master slave control is enabled CON EN 0 Programming Mode CON Control Register Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN MS 0 A REN BEN PEN REN TEN LB PO PH...

Страница 396: ...e errors BEN 11 rw Baudrate Error Enable 0 Ignore baudrate errors 1 Check baudrate errors AREN 12 rw Automatic Reset Enable 0 No additional action upon a baudrate error 1 The SSC is automatically rese...

Страница 397: ...r Flag 0 No error 1 Transfer starts with the slave s transmit buffer not being updated RE 9 rwh Receive Error Flag 0 No error 1 Reception completed before the receive buffer was read PE 19 rwh Phase E...

Страница 398: ...icate that register TB may be reloaded again When the programmed number of bits 2 16 has been transferred the contents of the shift register are moved to the Receive Buffer RB and the Receive Interrup...

Страница 399: ...Starting with the MSB CON HB 1 allows operation compatible with the SPI interface Regardless of the data width selected and whether the MSB or the LSB is transmitted first the transfer data is always...

Страница 400: ...ted to the external transmit line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the...

Страница 401: ...master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until...

Страница 402: ...ut line RXD This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift registe...

Страница 403: ...ved between arbitrary stations Similar to Full Duplex Mode there are two ways to avoid collisions on the data exchange line only the transmitting device may enable its transmit pin driver the non tran...

Страница 404: ...without any additional delay On the data line there is no gap between the two successive frames For example two byte transfers would look the same as one word transfer This feature can be used to inte...

Страница 405: ...Generator Reload register Reading BR while the SSC is enabled returns the content of the timer Reading BR while the SSC is disabled returns the programmed reload value In this mode the desired reload...

Страница 406: ...ible baudrates together with the required reload values and the resulting bit times assuming a module clock of 60 MHz Field Bits Type Description BR_VALUE 15 0 rw Baudrate Timer Reload Register Value...

Страница 407: ...t rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear...

Страница 408: ...cted A Transmit Error Slave Mode is detected when a transfer was initiated by the master SS_CLK gets active but the transmit buffer TB of the slave was not updated since the last transfer This conditi...

Страница 409: ...optionally be configured as reload or capture registers for the core timer Block 2 contains two timers counters with a maximum resolution of fclk 2 An additional CAPREL register supports capture and...

Страница 410: ...am Note Bus Peripheral Interface BPI is the connection to the on chip bus system GPT12E Module Interrupt Control Port Control Clock Control Address Decoder Kernel fclk T3OUT BPI Module Product Interfa...

Страница 411: ...catenation of T3 with other timers is provided through line T3OTL The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 locat...

Страница 412: ...Structure of Timer Block 1 T3 Mode Control T2 Mode Control GPT1 Timer T2 Reload Capture Prescaler T4 Mode Control GPT1 Timer T4 Reload Capture GPT1 Timer T3 T3OTL U D T2EUD T2IN T3IN T3EUD T4IN T4EUD...

Страница 413: ...1 6 2001 08 12 2 1 Core Timer T3 The operation of core Timer T3 is controlled by its bitaddressable control register T3CON T3 Timer 3 Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T3 rwh Fie...

Страница 414: ...ntal Interface Mode see Table 12 5 for encoding T3M 5 3 rw Timer 3 Mode Control 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100...

Страница 415: ...Latch Toggles on each overflow underflow of T3 Can be set or reset by software BPS1 12 11 rw Timer Block Prescaler 1 The maximum input frequency1 00 Timer Block 1 is fclk 8 01 Timer Block 1 is fclk 4...

Страница 416: ...ne T3EUD is used as external count direction control input its associated port pin must be configured as input Note The direction control works the same way for core Timer T3 and for auxiliary Timers...

Страница 417: ...he following formula Note BPS1 represents the prescaler value of the prescaler part controlled by bitfield BPS1 For the values see the bit description in register T3CON Table 12 2 Timer 3 Input Parame...

Страница 418: ...Timer T3 is selected by setting bitfield T3M in register T3CON to 010B or 011B Bit T3M 0 T3CON 3 selects the active level of the gate input The same options for the input frequency are available in G...

Страница 419: ...cleared or the gate is inactive Note A transition of the gate signal at line T3IN does not cause an interrupt request Timer 3 in Counter Mode Counter Mode for core Timer T3 is selected by setting bit...

Страница 420: ...e Mode Incremental Interface Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to 110B or 111B In Incremental Interface Mode the two inputs associated with Timer T3 T3IN T3E...

Страница 421: ...for Timer T3 occurs Count direction changes in the count direction and count requests are monitored by status bits T3RDIR T3CHDIR and T3EDGE in register T3CON T3 is modified automatically according t...

Страница 422: ...l direction control The maximum input frequency allowed in Incremental Interface Mode is fclk 8 T3BPS 01B To ensure that a transition of any input signal is correctly recognized its level should be he...

Страница 423: ...s current position Dynamic information speed acceleration deceleration may be obtained by measuring the incoming signal periods T3IN T3EUD Contents of T3 Forward Forward Backward Jitter Jitter U p D...

Страница 424: ...rwh Field Bits Typ Description Tx 15 0 rwh Timer x Contains the current value of Timer x T2CON Timer 2 Control Register Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T2 RDIR T2 CH DIR T2 ED...

Страница 425: ...gate active low 011 Gated Timer Mode with gate active high 100 Reload Mode 101 Capture Mode 110 Incremental Interface Mode Rotation Detection Mode 111 Incremental Interface Mode Edge Detection Mode T...

Страница 426: ...y timers T2 and T4 can be handled by the associated run control bit T2R T4R in register T2CON T4CON Alternatively a remote control option T2RC T4RC set may be enabled to start and stop T2 T4 via the r...

Страница 427: ...gures and tables apply accordingly with two exceptions There is no TxOUT output line for T2 and T4 Overflow underflow monitoring is not supported no bit TxOTL in registers TxCON Table 12 7 Timer x Inp...

Страница 428: ...the triggering transition see Table 12 8 Note Only state transitions of T3OTL caused by the overflow underflow of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will...

Страница 429: ...gative transition of T3OTL are used to clock the auxiliary timer this timer is clocked on every overflow underflow of core Timer T3 Thus the two timers form a 32 bit timer 33 bit Timer Counter If eith...

Страница 430: ...When programmed for Reload Mode the respective auxiliary Timer T2 or T4 stops independently of its run flag T2R or T4R Figure 12 13 GPT1 Auxiliary Timer in Reload Mode Note Line is affected by over u...

Страница 431: ...iary timers allows very flexible Pulse Width Modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on...

Страница 432: ...n the respective register TxCON to 101B In Capture Mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer...

Страница 433: ...ntal Interface Mode When auxiliary Timers T2 and T4 are programmed to Incremental Interface Mode their operation is the same as described for core Timer T3 The descriptions figures and tables apply ac...

Страница 434: ...s the concatenation of T6 with auxiliary Timer T5 while concatenation of T6 with other timers is provided through line T6OUT Triggered by an external signal the contents of T5 can be captured into reg...

Страница 435: ...2001 08 Figure 12 17 Structure of Timer Block 2 MUX Prescaler fclk T5 Mode Control GPT2 Timer T5 Prescaler fclk T6 Mode Control GPT2 Timer T6 GPT2 CAPREL T6OTL T5EUD T5IN CAPIN T3IN T3EUD T6IN T6EUD U...

Страница 436: ...000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6 SR T6 CLR 0 BPS2 T6 OTL T6 OE T6 UDE T6 UD T6R T6M T6I rw rw r rw rwh rw rw rw rw rw rw Field Bits Typ Description T6I 2 0 rw Timer 6 Input Parameter Sele...

Страница 437: ...w underflow may be externally monitored via T6OUT T6OTL 10 rwh Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software BPS2 12 11 rw Timer Block Prescaler...

Страница 438: ...T6UD is set a high level at line T6EUD specifies counting up and a low level specifies counting down The count direction can be changed whether the timer is running or not Note The direction control w...

Страница 439: ...the following formula Note BPS2 represents the prescaler value of the prescaler part controlled by bitfield BPS2 For the values see the bit description in register T6CON Figure 12 18 Block Diagram of...

Страница 440: ...l A high level at this line stops the timer If T6M 0 1 line T6IN must have a high level to enable the timer Additionally the timer can be turned on or off by software using bit T6R The timer will run...

Страница 441: ...n at this line Bitfield T6I in control register T6CON selects the triggering transition see Table 12 12 Figure 12 20 Block Diagram of Core Timer T6 in Counter Mode Table 12 12 Core Timer T6 Counter Mo...

Страница 442: ...rmined by its bitaddressable control register T5CON Note that functions present in both timers of Timer Block 2 are controlled in the same bit positions and in the same manner in each of the specific...

Страница 443: ...Timer 5 Run Bit 0 Timer Counter 5 stops 1 Timer Counter 5 runs T5UD 7 rw Timer 5 Up Down Control when T5UDE 0 0 Counts Up 1 Counts Down T5UDE 8 rw Timer 5 External Up Down Enable 0 Counting direction...

Страница 444: ...e exceptions There is no T5OUT line for T5 There is no T5OFL line for T5 Overflow underflow monitoring is not supported no bit T5OTL CI 13 12 rw Register CAPREL Capture Trigger Selection depending on...

Страница 445: ...the output toggle latch T6OTL on Timer 6 Figure 12 21 Block Diagram of Auxiliary Timer T5 in Counter Mode Table 12 13 Timer 5 Input Parameter Selection Timer and Gated Timer Modes T5I Prescaler for fc...

Страница 446: ...is selected to clock auxiliary Timer T5 this concatenation forms a 32 bit or a 33 bit timer counter 32 bit Timer Counter If both a positive and a negative transition of T6OTL is used to clock auxiliar...

Страница 447: ...the external input line CAPIN or the input lines T3IN and or T3EUD of Timer T3 as the source for a capture trigger Either a positive a negative or both a positive and a negative transition at line CA...

Страница 448: ...from the input signals When a selected transition at the external input line CAPIN is detected the contents of auxiliary Timer T5 are latched into register CAPREL and interrupt request line CRIRQ is d...

Страница 449: ...e Timer T6 When Timer T6 overflows from FFFFH to 0000H when counting up or underflows from 0000H to FFFFH when counting down the value stored in register CAPREL is loaded into Timer T6 This will not d...

Страница 450: ...ode can be used to detect consecutive external events which may occur aperiodically but which require a finer resolution more ticks within the time between two external events For this purpose the tim...

Страница 451: ...mes more transitions than the signal applied to line CAPIN A certain deviation of the output frequency is generated by the fact that Timer T5 will count actual time units for example T5 running at 1 M...

Страница 452: ...User s Manual C166S V1 SubSystem General Purpose Timer Unit User s Manual 12 44 V 1 6 2001 08...

Страница 453: ...T 6 19 BXOR 6 20 CALLA 6 21 CALLI 6 22 CALLR 6 23 CALLS 6 24 CMP 6 25 CMPB 6 26 CMPD1 6 27 CMPD2 6 28 CMPI1 6 29 CMPI2 6 30 CPL 6 31 CPLB 6 32 DISWDT 6 33 DIV 6 34 DIVL 6 35 DIVLU 6 36 DIVU 6 37 EINIT...

Страница 454: ...User s Manual C166S V1 SubSystem Instruction Index User s Manual 13 2 V 1 6 2001 08...

Страница 455: ...9 BWT 3 37 C CAPREL 12 39 Capture Mode GPT2 12 39 Capture Reload Register 12 39 Central System Control 2 13 CGU 2 14 Chip Select Configuration 8 13 Latched Early 8 14 Clock Generation Unit 2 14 Concat...

Страница 456: ...2 8 11 G GPR 4 10 GPT1 12 3 GPT2 12 26 H Hold State 8 33 I ID Control 2 13 Idle State Bus 8 30 INC 3 36 3 37 Instruction Timing 3 87 Interface External Bus 8 1 Internal Bus 2 8 Interrrupt Control Regi...

Страница 457: ...S0TIC S0TBIC 10 23 S0RBUF 10 13 10 15 S0TBUF 10 11 10 15 SCU 2 12 Segment Address 8 12 boundaries 4 9 Serial Interface Asynchronous 10 9 Synchronous 10 14 SFR 4 5 SFR Table ordered by address 4 12 SF...

Страница 458: ...er Mode 12 9 Timer 4 Capture Mode 12 24 Timer 4 Control Register 12 16 Timer 4 Counter Mode 12 20 Timer 4 Gated Mode 12 19 Timer 4 Incremental Interface 12 25 Timer 4 Reload Mode 12 22 Timer 4 Timer M...

Страница 459: ......

Страница 460: ...es and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulne...

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