Infineon C166S V1 SubSystem, Руководство пользователя

Страница: 442 / 460

User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
User’s Manual 12-34 V 1.6, 2001-08
The maximum input frequency allowed in Counter Mode is f
clk
/4 (BPS2 = ’01’). To ensure
that a transition of the count input signal applied to T6IN is correctly recognized, its level
should be held high or low for at least 2
f
clk
cycles (BPS2 = ’01’) before it changes.
12.3.2 Auxiliary Timer T5
The auxiliary Timer T5 can be configured for Timer Mode, Gated Timer Mode, or Counter
Mode with the same options for the timer frequencies and the count signal as core Timer
T6. In addition to these three counting modes, the auxiliary timer can be concatenated
with the core timer.
The individual configuration for Timer T5 is determined by its bitaddressable control
register T5CON. Note that functions present in both timers of Timer Block 2 are
controlled in the same bit positions and in the same manner in each of the specific control
registers.
Run control for auxiliary Timer T5 can be handled by the associated Run Control Bit T5R
in register T5CON. Alternatively, a remote control option (T5RC is set) may be enabled
to start and stop T5 via the run bit T6R of core Timer T6.
Note: The auxiliary timer has no bit T5OTL. Therefore, an output line for overflow/
underflow monitoring is not provided.
T5
Timer 5
(Reset value: 0000
H
)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T5
rwh
Field Bits Typ Description
T5 [15:0] rwh Timer 5
Contains the current value of Timer 5.
T5CON
Timer 5 Control Register
(Reset value: 0000
H
)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T5
SC
T5
CLR
CI
T5
CC
CT3
T5
RC
T5
UDE
T5
UD
T5R T5M T5I
rw rw rw rw rw rw rw rw rw rw rw