Infineon C166S V1 SubSystem, Руководство пользователя

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User’s Manual
C166S V1 SubSystem
Asynchronous/Synchronous Serial Interface (ASC)
User’s Manual 10-21 V 1.6, 2001-08
Note: ApNote AP2423 provides a program ’ASC.EXE’ which allows calculation of
values for the FDV and BG registers depending on f
clk
, the requested baudrate,
and the maximum deviation.
10.3.3.2 Baudrate in Synchronous Mode
For synchronous operation, the baudrate generator provides a clock with four times the
rate of the established baudrate.(see
Figure 10-10 ).
Table 10-3 Asynchronous Baudrate Formulas using the Fractional Input Clock
Divider
FDE BRS BG FDV Formula
1 - 1 ... 8191 1 ... 511
0
Table 10-4 Typical Asynchronous Baudrates using the Fractional Input Clock
Divider
f
clk
Desired
Baudrate BG FDV Resulting
Baudrate Deviation
40 MHz 115.2 kBaud 15
H
1F7
H
115.214 kBaud 0.01 %
57.6 kBaud 26
H
1F7
H
57.607 kBaud 0.01 %
38.4 kBaud 41
H
1F7
H
38.404 kBaud 0.01 %
19.2 kBaud 83
H
1F7
H
19.202 kBaud 0.01 %
60 MHz 115.2 kBaud 20
H
1F7
H
115.214 kBaud 0.01 %
57.6 kBaud 41
H
1F7
H
57.607 kBaud 0.01 %
38.4 kBaud 61
H
1FD
H
38.415 kBaud 0.04 %
19.2 kBaud C5
H
1FD
H
19.207 kBaud 0.04 %
FDV
16 x (BG+1)
Baudrate =
f
clk
512
x
16 x (BG+1)
Baudrate =
f
clk