Infineon C166S V1 SubSystem, Руководство пользователя

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User’s Manual
C166S V1 SubSystem
The External Bus Interface
User’s Manual 8-32 V 1.6, 2001-08
access to the external bus. All actions that just require internal resources such as
instruction, data memory, or on-chip peripherals may be executed in parallel.
When the C166S needs access to its external bus while it is occupied by another bus
master, it demands it via the BREQ output.
The external bus arbitration is enabled by setting bit HLDEN in register PSW to 1. The
three bus arbitration pins HOLD, HLDA, and BREQ will be controlled automatically by
the EBC independent of their I/O configuration. Bit HLDEN may be cleared during the
execution of program sequences in which the external resources are required but cannot
be shared with other bus masters. In this case, the C166S will not answer to HOLD
requests from other external masters. If HLDEN is cleared while the C166S is in hold
state (code execution from internal RAM/ROM), this hold state is left only after HOLD
has been deactivated again. The current hold state will continue and only the next HOLD
request is not answered.
Connecting two C166Ss in this way would require additional logic to combine the
respective output signals HLDA and BREQ. This can be avoided by switching one of the
controllers into Slave Mode, in which pin HLDA is switched to input. This allows the slave
controller to be connected directly to another master controller without glue logic. The
Slave Mode is selected by setting bit DP6.7 to ’1’. DP6.7=’0’ (default after reset) selects
the Master Mode.
Note: The pins HOLD, HLDA and BREQ keep their alternate function (bus arbitration)
even after the arbitration mechanism has been switched off by clearing HLDEN.
All three pins are used for bus arbitration after bit HLDEN has been set once.
Connecting Bus Masters
When multiple C166Ss or a C166S and another bus master share external resources,
some glue logic is required to define the currently active bus master, and to enable a
PSW
Processor Status Word
SFR(FF10
H
,88
H
) Reset value: 0000
H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILVL IEN
HLD
EN
0 0 0 USR0
MUL
IP
E Z V C N
rwh
rw rw r r r rw rwh rwh rwh rwh rwh rwh
Field Bits Type Description
HLDEN [10] rw External Bus Arbitration Control
0
H
External arbitration disabled
1
H
External arbitration enabled