Infineon C166S V1 SubSystem, Руководство пользователя

Страница: 391 / 460

User’s Manual
C166S V1 SubSystem
High-Speed Synchronous Serial Interface (SSC)
User’s Manual 11-1 V 1.6, 2001-08
11 High-Speed Synchronous Serial Interface (SSC)
11.1 Introduction
The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-
duplex serial synchronous communication up to 30 MBaud (@ 60 MHz module clock).
The serial clock signal can be generated by the SSC itself (Master Mode) or can be
received from an external master (Slave Mode). Data width, shift direction, clock polarity,
and phase are programmable. This allows communication with SPI-compatible devices.
Transmission and reception of data is double-buffered. A 16-bit baudrate generator
provides the SSC with a separate serial clock signal.
Features:
• Master and Slave Mode operation
– Full-duplex or half-duplex operation
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Baudrate generation from 30 MBaud to 457.76 Baud (@ 60 MHz module clock)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baudrate, transmit error)