Infineon C166S V1 SubSystem, Руководство пользователя

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User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
User’s Manual 12-3 V 1.6, 2001-08
12.2 Functional Description of Timer Block 1
All three timers of Block 1 (T2, T3, T4) can run in four basic modes: Timer Mode, Gated
Timer Mode, Counter Mode, and Incremental Interface Mode. All timers can count up or
down. Each timer of Block 1 is controlled by a separate control register TxCON.
Each timer has an input line, TxIN, associated with it which serves as the gate control in
Gated Timer Mode, or as the count input in Counter Mode. The count direction (up/down)
may be programmed via software or may be dynamically altered by a signal at an
external control line, External Up/Down Control Input TxEUD. An overflow/underflow of
core Timer T3 is indicated by the Output Toggle Latch T3OTL whose state may be output
on related signal line T3OUT. Additionally, the auxiliary timers T2 and T4 may be
concatenated with core Timer T3 or may be used as capture or reload registers for core
Timer T3. Concatenation of T3 with other timers is provided through line T3OTL.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer registers, T2, T3, or T4, located in the non-bitaddressable Special
Function Register (SFR) space. When any of the timer registers is written by the CPU in
the state immediately before a timer increment, decrement, reload, or capture is to be
performed, the CPU write operation has priority in order to guarantee correct results.
From a programmer’s point of view, the GPT1 block is composed of a set of SFRs as
summarized below. Those registers which are not part of the GPT1 block are shaded.
Figure 12-2 SFRs associated with Timer Block GPT1
All GPT1 registers are located in the SFR/ESFR memory space. The respective SFR
addresses can be found in list of SFRs.
T4IC
T2IC
T3IC
T2CON
T3CON
T4CON T4
T3
T2
T2 Timer 2 Register
T3 Timer 3 Register
T4 Timer 4 Register
T2ICTimer 2 Interrupt Control Register
T3ICTimer 3 Interrupt Control Register
T4ICTimer 4 Interrupt Control Register
Data Registers Control Registers Interrupt Control
T2CONTimer 2 Control Register
T3CONTimer 3 Control Register
T4CONTimer 4 Control Register