Infineon C166S V1 SubSystem, Руководство пользователя

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User’s Manual
C166S V1 SubSystem
The External Bus Interface
User’s Manual 8-36 V 1.6, 2001-08
the standard ADDRSEL registers. As the register pairs control integrated peripherals
rather than externally connected ones, most of the registers are fixed by mask
programming rather than being user-programmable.
The XBUS provides byte-wide or word-wide X-Peripheral accesses. Because the on-
chip connection can be very efficient, and for performance reasons, X-Peripherals are
implemented only with a separate address bus, i.e., in demultiplexed bus mode. Interrupt
nodes are provided for X-Peripherals to be integrated.
Enabling XBUS Peripherals
After reset, all on-chip XBUS peripherals are disabled. An XBUS peripheral cannot be
used unless it has been enabled via the global enable bit XPEN in register SYSCON.
Additional to the XPEN bit, the XPERCON register define which on-chip peripherals are
enabled or disabled (xpercon_o[15:0]). If a peripheral is disabled all it’s addresses are
no more visible.
The XPERCON register is accessible until execution of the EINIT instruction.
XPER selection with the XPERCON register has to be performed before the selected X-
peripherals are globally enabled via XPEREN-bit in SYSCON Register.
XPERCON
XPeripheral Control Register
SFR (F024
H
/12
H
) Reset value: 0000
H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
15
PER
14
PER
13
PER
12
PER
11
PER
10
PER
9
PER
8
PER
7
PER
6
PER
5
PER
4
PER
3
PER
2
PER
1
PER
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Field Bits Type Description
PER0 [0] rw XPeripheral Enable Control for XCS1
0
XPeripheral disabled
1 XPeripheral enabled
PER1 [1] rw XPeripheral Enable Control for XCS2
0
XPeripheral disabled
1 XPeripheral enabled
PER2 [2] rw XPeripheral Enable Control for XCS3
0
XPeripheral disabled
1 XPeripheral enabled
PER3 [3] rw XPeripheral Enable Control for XCS4
0
XPeripheral disabled
1 XPeripheral enabled