Infineon C166S V1 SubSystem, Руководство пользователя

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User’s Manual
C166S V1 SubSystem
General Purpose Timer Unit
User’s Manual 12-21 V 1.6, 2001-08
For counter operation, an external pin associated with line TxIN must be configured as
input. The maximum input frequency allowed in Counter Mode is
f
clk
/8 (BPS1 = ’01’). To
ensure that a transition of the count input signal applied to TxIN is correctly recognized,
its level should be held for at least 4
f
clk
cycles (BPS1 = ’01’) before it changes.
12.2.3 Timer Concatenation
Using T3OTL as a clock source for an auxiliary timer of Block 1 in Counter Mode
concatenates core Timer T3 with the respective auxiliary timer. Depending on which
transition of T3OTL is selected to clock the auxiliary timer, this concatenation forms a
32-bit or a 33-bit timer/counter.
• 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL are used
to clock the auxiliary timer, this timer is clocked on every overflow/underflow of core
Timer T3. Thus, the two timers form a 32-bit timer.
• 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected
to clock the auxiliary timer, this timer is clocked on every second overflow/underflow
of core Timer T3. This configuration forms a 33-bit timer (16-bit core
timer+T3OTL+16-bit auxiliary timer).
The count directions is not required to be the same in the two concatenated timers. This
offers a wide variety of different configurations. T3 can operate in Timer Mode, Gated
Timer Mode or Counter Mode in this case.
Figure 12-12 Concatenation of Core Timer T3 and an Auxiliary Timer
Note: Line ’*)’ is affected by over/underflow of T3 only, but NOT by software
modifications of T3OTL
Core Timer T3 T3OTL
T3IRQ
T3R
Prescaler
T3l
MCB02034_d
f
clk
Up/Down
Auxiliary Timer Tx
TxR
Txl
Edge
Select
TxIR TxIRQ
*)
BPS1
Up/Down
x = 2,4
TxIN
T3OE
T3OUT
MUX
0
1
1