Infineon C166S V1 SubSystem, Руководство пользователя

Страница: 341 / 460

User’s Manual
C166S V1 SubSystem
The External Bus Interface
User’s Manual 8-19 V 1.6, 2001-08
Figure 8-9 READY Controlled Bus Cycles
1)
Section 8.3.4 Read/Write Delay
2)
Section 8.3.5 Early Write
4)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
5)
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
6)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here. For a multiplexed bus with MTTC waitstate, this delay is 2 CLKOUT cycles; for a
demultiplexed bus without MTTC waitstate this delay is zero.
7)
If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first
valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current
cycle, and on the MCTC waitstates and the ALE mode of the next cycle. If the current cycle uses a multiplexed
bus, the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time.
The READY function is enabled via the ReaDY ENable (RDYENx) bits in the BUSCON
registers. When this function is selected (RDYENx = 1), only the lower 3 bits of the
respective MCTC bit field define the number of inserted waitstates (0-7), while the MSB
of bit field MCTC is unused:
As shown in Figure 8-9 , the asychronous READY requires additional waitstates caused
by the internal synchronization. The asynchronous READY is synchronized internally,
and programmed waitstates may be necessary to provide proper bus cycles (see also
notes on “normally-ready” peripherals below).
An asynchronous READY signal that has been activated by an external device may be
deactivated in response to the trailing (rising) edge of the respective command (RD or
WR).
Note: When the READY function is enabled for a specific address window, each bus
cycle within this window must be terminated with an active READY signal.
Otherwise, the controller hangs until the next reset. A time-out function is provided
by the watchdog timer.
The next
ext
ernal bus
CLKOUT
Command
(RD, WR)
Running Cycle
4)
1)
Asynch.
READY
READY-WS MUX/MTTC
5) 5)
6)
7) c
ycle my s
tart
here.
2)